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FEI4_A_OABUF Simulation: Minimizing Input Capacity & Optimizing Output Transistors in Marseille

Simulation setup for FEI4_A_OABUF, optimizing analog chain with OPAMP, lower input transistors dimension, and higher output transistors. Test with sensitive signals, minimizing input capacity, and loading CLOAD=20pF. Results for Out1 & Out2 with varying QIN levels.

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FEI4_A_OABUF Simulation: Minimizing Input Capacity & Optimizing Output Transistors in Marseille

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  1. FEI4_A_OABUF CPPM, Université de la méditerranée, CNRS/IN2P3, Marseille, France

  2. Symbol & I/O pins list

  3. Disc Out2 Out1 Preamp Amp2 In1 In2 20pF FEI4_A_OABUF In32 Simulation set up • Simulation with the biased analog chain • Test with sensitive signals (Out1 & Out2) • CLOAD=20pF • MUX32to1 = 4xMUX8to1 + MUX4to1 • To minimize the input equivalent capacity of Cell • OPAMP • Input transistors with lower dimension • To minimize the input capacity of amplifier • output transistors with higher dimension • To load 20pF CLOAD • GBWP 30MHz → 50MHz

  4. Out2 results (1/2) Out2 for 2ke-<QIN<22ke-

  5. Out2 results (2/2) ≠max 1mV ≠max 2ns

  6. Out1 results (1/2) Out1 for 2ke-<QIN<22ke-

  7. Out1 results (2/2) ≠max 1mV ≠max 6ns

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