Transaction Level Modeling of Reconfigurable SOC : Hardware/Software task scheduling

1. International Conference on Computing, Communications and Control Technologies: CCCT'04 August 14-17, 2004 - Austin, Texas, USA Transaction Level Modeling ofReconfigurable SOC :Hardware/Software task scheduling Hassan RABAH Hassan.Rabah@lien.uhp-nancy.fr Laboratoire d'Instrumentation Électronique de Nancy Université Henri Poincaré BP 234 54506 Vandœuvre-les-Nancy France

2. Outline • Introduction • Motivations • Basic concept • Modeling Reconfiguration • Case Study • Conclusion Hassan RABAH — CCCT04

3. FPGA Soft Core1 hard Core µP µP µP VGA Audio USB PCI FireWire Soft Core2 FPGA VGA VGA Audio Audio USB USB PCI PCI FireWire FireWire Microprocessor(s) MPEG Ethernet µP µP Memory ASIC RAM Microprocessor Microprocessor DSP DSP Ethernet Ethernet IR JTAG Soft Core2 IR IR Configurable fabric RAM LED FPGA FPGA RAM RAM LED LED JTAG • RSoC Characteristics • High level of integration • Complex modules and IP reuse JTAG JTAG Introduction| Motivations | SystemC & TLM basics | Modeling Reconfiguration | Case Study | Conclusion • Systems complexity Performance ideal chip ASIC FPGAs GPP Flexibility • Need a better abstraction and modeling • Formal proof of Specification (proved design) • System modeling in different levels of abstraction (model refinement) • Virtual platform for system validation in early stage of design Hassan RABAH — CCCT04

4. M3 M1 M2 • Virtual platform (PE, memory, RL..) • Modules • HW/SW/CW • Communication channels • Bus, fifo, … M5 M4 M6 Introduction| Motivations | SystemC & TLM basics | Modeling Reconfiguration | Case Study | Conclusion • Virtual platform (design validation) • RSoC design and Verification problems • Use of different languages (UML, B, C, C++, VHDL, ...) • Formal model / implementation • Hardware/software teams • Simulation time too long • Not error free • Adopted Solution • Unified design flow • Proved specification  implementation • SystemC: OO, different levels of abstraction • Transaction level Model architecture exploration Hassan RABAH — CCCT04

5. Specifications • Formal model of spec • High level description • “Proved” model • Incremental refinement Formal model • Functional Model • SystemC model • Functional validation • Overall system verification Refinement UTF SystemC TF TLM • Partitioning • Hardware • Software • “Configware” Model checking Abstract RTOS BCA BCA • Verification • Simulation • Model checking *.asm, *.c RTL RTL Software Hardware Configware implementation Introduction| Motivations | SystemC & TLM basics | Modeling Reconfiguration | Case Study | Conclusion • Design flow Hassan RABAH — CCCT04

6. Introduction| Motivations | SystemC & TLM basics | Modeling Reconfiguration | Case Study | Conclusion • SystemC (not a language)(http://www.systemc.org 2.01) • C++ library aimed specifically at system level modeling • Object oriented design methodology • Defines primary channels for communicating transactions • TLM (basics) • Transaction: Exchange of data or event between modules of a modeled system • Module: Structural entity, which contain processes, ports, channels, and other modules • Channel: Implements one or more interfaces, and serves as a container for communication functionality • Port: Object through which a module can access a channel’s interface All these elements are exploited to build the virtual platform for RSoC validation. Hassan RABAH — CCCT04

7. Reconfigurable Fabric Conf. • Processing element • Software tasks( simple & complex functions) Arb • Reconfigurable logic • Hardware tasks (hw operators) • Memory • Configurations (HW) • Data • Programs (SW) PE1 PE2 Mem1 Mem2 • Configurator • Scheduling Hardware tasks • Channels • Communication tasks • Arbiter • Conflicts arbitrations Introduction| Motivations | SystemC & TLM basics | Modeling Reconfiguration | Case Study | Conclusion • Reconfigurable SoC paltform PE1->bus_port(*bus); PE2->bus_port(*bus); Confi->bus_port(*bus); Fab->bus_port(*bus); bus->arbiter_port(*arbiter); bus->slave_port(*mem1); bus->slave_port(*mem2); Hassan RABAH — CCCT04

8. Reconfigurable fabric • Running hardware tasks • acceleration • Transaction • PE, memory Conf. Conf. tsk1 tsk1 tsk2 tsk2 tsk3 Arb Arb • Configurator • Scheduler • Hardware tasks • Configure device • Full reconfiguration • Partial reconfiguration • Transaction • Configuration memory PE1 PE2 Mem1 PE1 PE2 Mem1 Mem2 Mem2 Introduction| Motivations | SystemC & TLM basics | Modeling Reconfiguration | Case Study | Conclusion Reconfiguration scenario new state of the system Hassan RABAH — CCCT04

9. tsk3 Conf. tsk1 tsk2 Introduction| Motivations | SystemC & TLM basics | Modeling Reconfiguration | Case Study | Conclusion Elements of the model • Reconfigurable fabric • Pool of threads • HW task : method • Concurrency • Fork/Join • Dynamic reconfiguration • Full reconfiguration • Partial reconfiguration • Configurator • State machine (scheduler) • load hardware task • flush hardware tasks Hassan RABAH — CCCT04

10. First configuration SC_FORK sc_spawn_method(&r, this, &Fab0::Hardware1, "1", &e1, &e3, x ), sc_spawn_method(&r, this, &Fab0::Hardware2, "2", &e1, &e4, y ), SC_JOIN tsk1 tsk1 tsk3 Second configuration tsk2 SC_FORK sc_spawn_method(&r, this, &Fab0::Hardware1, "1", &e2, &e3, z ), sc_spawn_method(&r, this, &Fab0::Hardware3, “3", &e2, &e4, t ), SC_JOIN Input event Hardware: functionality of a task latency Execution time Input events: modeling latency of configuration Configuration Execution Output event Output event : modeling the execution time of a task Introduction| Motivations | SystemC & TLM basics | Modeling Reconfiguration | Case Study | Conclusion • Dynamic reconfiguration (SC_FORK SC_JOIN) Hassan RABAH — CCCT04

11. sc_join_handle h1; sc_join_handle h2; h1=sc_spawn_method(&r, this, &Fab0::Hardware1, "1", &e1, &e11, 1 ); h2=sc_spawn_method(&r, this, &Fab0::Hardware2, "2", &e1, &e12, 1 ); tsk3 tsk1 sc_process_join(h1); sc_join_handle h3; tsk2 h3= sc_spawn_method(&r, this, &Fab0::Hardware3, “3", &e2, &e13, 1 ); Conf1 Exec1 Conf2 Exec2 Exec2 Exec2 Conf3 Exec3 Introduction| Motivations | SystemC & TLM basics | Modeling Reconfiguration | Case Study | Conclusion • Partial dynamic reconfiguration Hassan RABAH — CCCT04

12. Introduction| Motivations | SystemC & TLM basics | Modeling Reconfiguration | Case Study | Conclusion QoS in DVB-T supervision and monitoring • QoS measurement in DVB-T • Transport stream • Video • Audio • System • Task identification • From specifications • Formal proof • Task dependency • Resources • Interdependence • Task characterization • Time constraints Hassan RABAH — CCCT04

13. TS packets Sync_byte_err transport err TS_sync_loss PID detect PAT PMT CAT NIT RST DATA TDT TDT_error RST_error CAT_error PAT_error Unreferenced PID NIT_actual_err RST_error_struct NIT_other_err PCR Continuity_system_error Continuity counter Update Continuity counter PCR_reception_error Update tables Clock recovery PCR_discontinuity indicator_error PCR_accuracy_error Bit rate measurement T-STD PCR Related measurement Service Performance evaluation Introduction| Motivations | SystemC & TLM basics | Modeling Reconfiguration | Case Study | Conclusion • Task graph • How to map tasks ? The use of reconfigurable platform. Hassan RABAH — CCCT04

14. Introduction| Motivations | SystemC & TLM basics | Modeling Reconfiguration | Case Study | Conclusion • Example : implementation of PCR related measurementandTransport Stream Target decoder • PCR related measurement (clock recovery, jitter measurement and other parameters) • Implementation of PLL • High rate (27MHz) • HW • Implementation of Filters • Low rate (10 ms rate of PCR arrival) • SW TS packets PCR PCR_reception_error • T-STD • Buffers management • Program • Video • Audio • System • architecture exploration Clock recovery PCR_discontinuity indicator_error PCR_accuracy_error T-STD PCR Related measurement Hassan RABAH — CCCT04

15. First configuration: configure device; wait data arrival LF: 2 configurations : 1TSTD+1PCR; 1TSTD+3PCRs Concurrent execution of hardware tasks And dynamic reconfiguration Tasks activation with data arrival PE1: direct transfer to LF Concurrent execution of hardware tasks Time execution / task Data transfer LF  Memory ( burst mode) PE2: software tasks +memory read/write (bus access) Introduction| Motivations | SystemC & TLM basics | Modeling Reconfiguration | Case Study | Conclusion • Simulation results Hassan RABAH — CCCT04

16. Introduction| Motivations | SystemC & TLM basics | Modeling Reconfiguration | Case Study | Conclusion • Reconfigurable platform • Help Scheduling of different tasks • Generation of scheduler • Tasks communication • Overall system validation • Architecture exploration • Hardware/software/configware • Link between formal specification and physical implementation • Future Works • From specification • Automatic generation of tasks • Platform integration of generated tasks • From target architecture • Timing • area • Energy/Power Hassan RABAH — CCCT04

17. International Conference on Computing, Communications and Control Technologies: CCCT'04 August 14-17, 2004 - Austin, Texas, USA Thank you Laboratoire d'Instrumentation Électronique de Nancy Université Henri Poincaré BP 234 54506 Vandœuvre-les-Nancy France