A True-Zero Load Stable Capacitor-Free CMOS Low Drop-out Regulator with Excessive Gain Reduction

1. A True-Zero Load Stable Capacitor-Free CMOS Low Drop-out Regulator with Excessive Gain Reduction Presented at ICECS 2010 December 15, 2010 John Hu and Mohammed Ismail The Analog VLSI Laboratory The Ohio State University

2. Outline • Introduction • Issue: Capacitor-Free Low Drop-Out (LDO) • Problem: True-Zero Load Stability • Approach • Method: Excessive Gain Reduction • Schematic Design • Results • Simulations • Measurements • Conclusion

3. Capacitor-Free LDO Regulator • External capacitor-free low drop-out (LDO) regulators are popular because of the benefit in space and cost iPhone 4, 2010. iPhone 3G, 2009.

4. True Zero-Load Stability • Conventional Miller-based pole splitting topologies suffer from zero-load oscillation • There is a short-cut solution:requiring a minimum Iout • Drawbacks • Standby efficiency degradation

5. Proposed Method • Observation:not all DC gain contributes to Miller Effect • Excessive Gain (G1)Reduction • Given the same totalDC gain, morecan be distributedto G2 and G3 toenhance the Miller effect

6. Schematic Design • Conventional: • G1: opamp • G2: positivegain stage • G3: MPT • Proposed: • G1’ • G2’: positivegain stage • G3’: MPT

7. Simulations: Bode Plot

8. Simulations: Load Transient • Load Regulation: (conventional vs. proposed) • Both are stable when power is unlimited • Only the proposed is stable during true zero-load (sleep mode)

9. Conclusion from Simulations • Power Efficiency Improvement • When true zero-load stability (TZLS) is required (sleep mode), the proposed method reduces the battery current by 67.5% [2] • Area efficiency • Conventional: 23 pF to achieve true zero-load stability [3] • Proposed: 4.5 pF [4]

10. Chip Fabrication • A dual-core LDO was fabricated in MOSIS 0.5 um CMOS under the same specs • One conventional, one proposed.

11. Test Board • PCB with off-chip load test solutions • High power rating resistors, NMOS, “stay alive” Ioutmin options:

12. Test Setup • Test Equipment and Connections

13. Measurement Results • Transient load regulation (conventional): • Vin=3.7 V, Vout=3.5 V. Stability with “stay alive” current.

14. Measurement Results • Transient load regulation: • 50% chance of over current (Iout > 1 A, chip heats up.) • Reason: gate of the PMOS pass element floating: top level layout error • Correlation with simulation

15. Conclusion • Conclusions • A true zero-load stable CMOS capacitor-free low drop-out regulator is presented • It reduces the excessive gain (G1) and re-distributes the gain to Miller-enhancing stages (G2, G3) • As a result, system power efficiency during standby can be improved by 67.5% • Future Work • Further analysis of the excessive gain reduction technique and battery life extending IC design methods • Lessons learned for future first-time-right silicon

16. Selected References • K. N. Leung and P. Mok, “A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation”, IEEE J. Solid-State Circuits, vol. 38, no. 10, pp. 1691-1702, Oct. 2003 • S. K. Lau, P. K. T. Mok, and K. N. Leung, “A low-dropout regulator for SoC with Q-reduction”, IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 658-664, Mar. 2007 • R. Milliken, J. Silva-Martinez, and E. Sanchez-Sincencio, “Full on-chip CMOS low-dropout voltage regulator”, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no.9, pp. 1879-1890, Sep. 2007 • J. Hu, W. Liu, and M. Ismail, “Sleep-mode ready, area-efficient capacitor-free low-dropout regulator with input current-differencing”, Analog Integrated Circuits and Signal Processing, vol. 63, no.1, pp.107-112, Apr. 2010

17. Thank you!