Hamming Code Design and Implementation: Error Detection and Correction in Telecommunication Systems

Hamming Code Clarissa David Timmy Lau WingChing Lin Jonathan Lee Advisor: Dr. David Parent December 7, 2005

Agenda • Abstract • Introduction • Why a Hamming Code? • Potential Applications • Theory of Operation • Calculations • Cadence Details • Summary of Results • Cost Analysis • Conclusions

Abstract • Target Specification • Clock Frequency: 200MHz • Load Capacitance: 30fF • Area: 900x500 micron squared • Actual Specification • Clock Frequency: 160MHz • Load Capacitance: 30fF • Area: 932.55 x 915.45 micron squared

Introduction • Hamming Code • Detects single and double-bit errors • Application • Telecommunication (i.e. networking) • Theory • Using 4 data bits, can generate 3 correction bits giving a total of 7 bits • Can correct any single bit error

Longest Path

Schematic Note: This is an Error Generator Gate Level Schematic of Hamming Code

Schematic Block schematic of Hamming without the flip-flop

Schematic Schematic of Hamming Code with flip-flop at the start

Layout Layout of Hamming Code

Verification: DRC Verification of DRC Passing

Verification: LVS Verification of LVS: PASSED!!!!

Simulation NCVerilog of Hamming Code Logic

Simulation

Simulation Simulation of Hamming Code with flip-flop

Simulation Simulation of error generator

Cost Analysis But from us….. FREE!!!!!

Lessons Learned • EXPOSE YOURSELF TO THE PROJECT EARLY • Be organized about your routing • Debugging layout • Work together as a team • EXPOSE YOURSELF TO THE PROJECT EARLY !!!

Summary Complete Circuit • Clock Frequency: 160MHz • Area: 932.55 x 915.45 microns squared • Load Capacitance: 30fF

Acknowledgements • Thanks to Cadence Design Systems • Thanks to Professor David Parent • Thanks to the current and past students of EE166

Hamming Code Design and Implementation: Error Detection and Correction in Telecommunication Systems