Understanding Pipeline Execution and Register Operations in MIPS Architecture
This document delves into the detailed analysis of register operations and instruction execution in a MIPS pipeline architecture. It outlines various operations such as reading and writing to registers, ALU control signals, memory read/write processes, and determining the effects of specific instructions on register states. Key examples of operations like Load Word (LW), Addition, and logical operations (AND, OR) are examined, highlighting how initial conditions such as program counter (PC) values and register contents affect output during execution. This study aids in grasping the fundamental concepts in computer architecture and assembly language programming.
Understanding Pipeline Execution and Register Operations in MIPS Architecture
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Presentation Transcript
1 0 Registers Read reg. num A Read reg num A Read reg data A Read reg num B Write reg num Read reg data B Write reg data 0 1 Problem HW8-2 –Name each identified portion of the registers and indicate # of bits Branch Target [32] PCSrc 4 Branch PC+4 Result Result Add MemToReg Sh.Left2 RegWrite Add MemWrite Rs:[25-21] Read address Rt:[20-16] Data Memory ALUSrc Read address PC Zero Read data 1 Instruction [31-0] Write address Result InstructionMemory 0 0 Write data 1 Imm:[15-0] MemRead ALUcontrol 16 32 signextend Rt:[20-16] Rd:[15-11] ALUOp RegDest
Problem HW8-3 – Give value for each register portion indicated 1 0 Registers Read reg. num A Read reg num A Read reg data A Read reg num B Write reg num Read reg data B Write reg data 0 1 LW $10,20($1)(from mem[31]) Add $14,$8,$9 Or $13, $6, $7 And $12,$4,$5 Sub $11,$2,$3 1100 1100 E 000 PCSrc Control 000 000 M M ‘OR’=0 10 10 11 10 W W W 4 0 Branch PC+4 Result Result Add Sh.Left2 Add RegWrite 1 0 MemToReg MemWrite 6 Read address 1 7 Data Memory Read address PC ALUSrc Zero Read data 1 Instruction [31-0] 0 Write address Result InstructionMemory 0 0 Write data 1 • Initial Conditions (before any instructions are executed): • PC=50010 (address ofLW instruction) • Each register has the value 10+register number. For example $5 = 15. • Memory locations have the value 100010+byte address of the word. For example Mem[8]=1008. Imm:[15-0] ALUcontrol 16 32 signextend 0 MemRead Rt:[20-16] 10 11 10 12 13 ALUOp RegDest 1 Execute stage signal ordering: RegDest, ALUOp1, ALUOp0, ALUSrcMemory stage signal ordering: Branch, MemRead, MemwriteWriteback stage signal ordering: RegWrite, MemToReg
Problem HW8-4 – Find out all you can about the five instructions in the pipeline 1 0 Registers Read reg. num A Read reg num A Read reg data A Read reg num B Write reg num Read reg data B Write reg data 0 1 Execute stage signal ordering: RegDest, ALUOp1, ALUOp0, ALUSrcMemory stage signal ordering: Branch, MemRead, MemwriteWriteback stage signal ordering: RegWrite, MemToReg 0001 1100 E 100 PCSrc Control 001 000 M M 10 00 11 00 W W W 4 1 Branch Result Result Add Sh.Left2 Add RegWrite 1 0 MemToReg MemWrite 10 Read address 15 1 11 Data Memory Read address PC ALUSrc Zero Read data 1 Instruction [31-0] 1 Write address Result 15 16 InstructionMemory 0 0 Write data 1 • Initial Conditions (before any instructions are executed): • PC=50010 (address ofrightmost instruction) • Each register has the value 10+register number. For example $5 = 15. • Memory locations have the value 100010+byte address of the word. For example Mem[8]=1008. ALUcontrol 16 16 32 signextend 2090 0 MemRead 6 11 31 15 0 1 00 ALUOp RegDest 0
