COMP541 Interrupts, DMA, Serial I/O

1. COMP541Interrupts, DMA, Serial I/O Montek Singh April 18, 2012

2. Interrupts • Two main kinds • Internal • Error when executing an instruction • Floating point exception • Virtual memory page fault • Trying to access protected memory • Invalid opcode! • System call requested by software • To request OS services • External • I/O

3. Internal • More complicated because two possible actions • may abort instruction • access to protected memory not allowed • or, OS corrects the situation and restarts instruction • e.g., virtual memory page fault • Question: • What happens for arithmetic overflow/divide-by-0?

4. When Interrupt Occurs • Interrupt enable register • Sometimes levels of interrupts individually enabled/disabled • PC is changed to new location • One or more interrupt locations stored • “vectored interrupts” • Or a fixed location • example: MIPS (e.g., 0xC000 0000) • Old PC saved to register or stack • Many machines have stack pointer

5. Registers • Sometimes registers saved by hardware • Some machines have one or more sets of registers • Often: software must save registers • Push them onto stack • Return from interrupt • Some CPUs provide a special instruction to return from interrupt • “rfi” or “iret” • Others use the standard procedure return instruction • jr, ret, etc. • Restore registers before returning

6. Cause of Interrupt • Need way to determine what caused interrupt • Note it can be more than one thing • Vectored Interrupts • Different types cause branches to different locations • Sometimes prioritized • Register to store cause • “Cause” register

7. Supervisory Mode • Modern computers have user mode and one or more “supervisory modes” • User mode restricted • Can’t write to many system registers, such as interrupt enable • Can’t write to some parts of memory • Usually I/O restricted • Interrupts cause switch to supervisory mode • In this mode, software has access to several privileged parts of the system • e.g.: kernel memory, IE register, etc. • Question: Which interrupts?

8. Some Interrupt Hardware • An example implementation • Interrupts ORed • Response if IE and at end of instruction • Ack interrupt • Vector address to PC • Save PC on stack

9. Potential Microcode The following is a typical sequence of actions taken by the CPU upon triggering of an interrupt: SP  SP – 1 M[SP]  PC SP  SP – 1 M[SP]  PSR • PSR is processor status register EI  0 INTACK  1 PC  IVAD

10. Return Similar • Very similar to return from procedure • Some additional actions • PSR holds IE bit • Restoring PSR turns interrupts on

11. Exception (from Patterson Hennessey, multicycle MIPS) PC – 4 stored Just two causes Branch to fixed addr Undefined instruction and arithmetic overflow

12. Restarting Instruction? • Imagine the interrupt (exception) was a page fault • Need to get the page, and then rerun the instruction • Keeping instructions simple/short helps out! • Otherwise may need to save some intermediate state • Imagine block-move instruction such as the Pentium MOVS • moves/copies an entire string (of variable length) in a single instruction!

13. Types of I/O Programmed I/O Direct Memory Access (DMA)

14. Direct Memory Access (DMA) • Programmed I/O is when CPU reads/writes every word • Problem: overhead is high; nothing else getting done on CPU • Especially for mass-storage devices like disk • DMA: Let device controller read/write directly to memory • CPU goes about its usual business of executing other instructions • typically cannot access memory while DMA is going on! • Challenges?

15. Protocol • DMA protocol • DMA device takes over main bus • Becomes bus master • Asserts addresses • Basically interfaces to memory or memory controller

16. How? • DMA device requests bus (assert BR) • CPU grants request (assert BG) • CPU takes its signals to Hi-Z • now DMA can use its signals to connect with memory • no conflict with CPU’s signals (they are floating)

17. Transfer Modes • Several types of transfer modes • Continuous: DMA controller transfers all data (say a disk sector) at once • As many memory cycles as data • Burst: DMA controller cycle steals, takes a cycle at end of every CPU instruction • Note: today’s processors are more sophisticated • there is a memory controller (“Northbridge”) • sits in-between CPU and memory • Why? Memories are more complex, caches, etc.

18. End of DMA • Controller needs to inform CPU • De-assert BR • Then CPU lowers BG and proceeds

19. DMA Controller • Needs typical I/O signals • Interrupt request • Status of device • Also needs controls for DMA transfer • Memory address • Word count

20. Block Diagram

21. Typical Driver Interface • Software drivers • Set the memory address • Set word count • Assert “GO” (usually bit in control word) • DMA controller starts copying … • … and requests interrupt when transfer complete

22. Trends in Communications • Older bus standards, such as ISA and PCI, were parallel (conventional “bus”) • Newer (PCI Express) use serial channels (lanes) • So slots for slower devices can be x1 • Slots for devices such as GPUs can be x16 (max x32 in spec) 16 lane PCI-E (below) 1 lane (right)

23. Disks • Change from ATA/IDE to SATA • IDE had 16 data channels • SATA has 2 twisted pair (xmit and recv)

24. RS-232/UART • Called “Asynchronous” • But both sides have precise clocks • Agree on speed • Receiver syncs during start bit

25. USB • One master • The PC • Idea was to have thin cables and plug and play • Specs include hardware and software • We only cover hardware

26. USB – Packet serial I/O • Four wires total • +5v and GND • Two signal wires • Twisted pair • Differential signaling • Differential 1 is D+ > 2.8v and D- < 0.3v • Differential 0 is opposite • Also a single-ended zero when D+ & D- low (end of packet, reset, disconnect)

27. Speed • Three speeds • High is 480 Mb/s • Full is 12 Mb/s • Low is 1.5 Mb/s • New Super Speed, 5Gb/s!! • Pull-up indicates full/low • High speed starts as full, then handshakes and transitions • High and low speeds interpret zeros and ones inverted.

28. Coding • NRZI • Non-Return to Zero Inverted • Transition if sending 0, none if sending 1 • Bit stuffing • Since a string of 1s causes no transitions, synchronization may be lost • A zero is stuffed in after six consecutive ones • Sync field • Each packet starts with a sync • 8 bits: 00000001

29. Packets • Won’t go into details

30. Summary • Many types of I/O • memory-mapped is most common • different devices given different address ranges • many different device protocols • PS/2: keyboard, mice • RS-232: serial ports • USB: most common today • also Firewire, Thunderbolt, … • ethernet • also monitors, displays • we did VGA (other higher resolutions also possible) • DVI is most common today

31. Conclusion of this course • What did we learn this semester? • Combinational logic • Sequential logic, finite-state machines • Basic building blocks • registers, counters • adders, subtractors, ALUs • memories, and memory-mapped I/O • datapaths • Verilog • hierarchical design • display interfaces, input devices, debouncing • CPUs • single-cycle, multicycle • pipelining, hazards, forwarding, stalling • Built an entire MIPS CPU!

32. Some Tips for your final project • Use MARS to assemble your program! • use: .text 0x80000000 • then simply copy all the machine code into your project • SLT • if you want to implement SLT, talk to me! • BEQ, BNE • make sure “delayed branching” is off in MARS • J • JAL, JR • not necessary, but could simplify your code • if you want to use procedure calls • PC=PC+4 (not 8) because our MIPS is unpipelined, no delayed jumps

33. Timeline • April 19 (Thu): • Test #1 graded, ready for pickup • April 20 (Fri): • First set of final project demos • HW #2 due • Test #2 (take home) released • April 23 (Mon): • Tentative grades for those already demo’ed • Second set of final project demos • Hw #2 due (last chance) • April 25 (Wed): • Tentative grades for those already demo’ed • Last chance to demo final project