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SDV : Dynamic Visualization of Verilog Simulations

2. SDV : Dynamic Visualization of Verilog Simulations. Ralph Marczynski ralphm@engr.smu.edu. Peter-Michael Seidel seidel@engr.smu.edu. Southern Methodist University Dallas, TX 75275. Computer Science and Engineering. Digital System Engineering. Design. Simulation. Schematic Entry.

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SDV : Dynamic Visualization of Verilog Simulations

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  1. 2 SDV : Dynamic Visualization of Verilog Simulations Ralph Marczynski ralphm@engr.smu.edu Peter-Michael Seidel seidel@engr.smu.edu Southern Methodist University Dallas, TX 75275 Computer Science and Engineering SDVSMU Dynamic Verilog Visualization

  2. Digital System Engineering Design Simulation Schematic Entry Text Waveform HDLs SDVSMU Dynamic Verilog Visualization

  3. 2 SDV : Motivation HDL Design SDV Simulation 2 Schematic Visualization Dynamic Signal Propagation Text Based Values/Time Structure Functionality SDVSMU Dynamic Verilog Visualization

  4. 2 SDV : Features & Functionality • Syntax-Error Free Verilog Hardware Description • Structural, Behavioral, or Mixed • Physically Feasible Design SDV 2 SDVSMU Dynamic Verilog Visualization

  5. 2 SDV : Features & Functionality • Module Selection • Module Placement / Geometry • Port Orientation • Lines Customization Visualization Configuration SDV 2 SDVSMU Dynamic Verilog Visualization

  6. 2 SDV : Features & Functionality Visualization and Animation Front-End SDV Visualization 2 Signal Propagation Text Output Visualization Configuration Veriwell 2.3 Command Line Simulator SDVSMU Dynamic Verilog Visualization

  7. 2 SDV : Sturcture & Implementation SIMULATION APPROACH Independent Atomic Module Simulations with Dynamic Variable Initialization vs. Complete System Simulation 2 Bit Ripple Carry Adder SDVSMU Dynamic Verilog Visualization

  8. 2 SDV : Sturcture & Implementation SIMULATION APPROACH Independent Atomic Module Simulations with Dynamic Variable Initialization vs. Complete System Simulation 2 Bit Ripple Carry Adder SDVSMU Dynamic Verilog Visualization

  9. 2 SDV : Sturcture & Implementation SIMULATION APPROACH Independent Atomic Module Simulations with Dynamic Variable Initialization vs. Complete System Simulation 2 Bit Ripple Carry Adder SDVSMU Dynamic Verilog Visualization

  10. 2 SDV : Sturcture & Implementation SIMULATION APPROACH Independent Atomic Module Simulations with Dynamic Variable Initialization vs. Complete System Simulation 2 Bit Ripple Carry Adder SDVSMU Dynamic Verilog Visualization

  11. 2 SDV : Sturcture & Implementation MODULE SIMULATION ORDER { Direct Connection Output Input Dependencies Continuous/Procedural Assignment Function/Task Determine Primitive/User Defined Primitive Simulation Order Guarantees Availability of Variables at Time Of Independent Module Simulation SDVSMU Dynamic Verilog Visualization

  12. 2 SDV : Sturcture & Implementation MODULE SIMULATION ORDER EXTRACTION 2 Step Extraction Procedure • Local Dependency Dependency Among Instantiations in a Defined Module • Global Dependency Top-Level Dependency Considering The Entire System Local Input/Output Instantiation Dependency SDVSMU Dynamic Verilog Visualization

  13. 2 SDV : Sturcture & Implementation MODULE SIMULATION ORDER In-Order Traversal Generates the Simulation Order 1. During Visit- inputs to the Instantiation are known Top-Level Local Input/Output Instantiation Dependency SDVSMU Dynamic Verilog Visualization

  14. 2 SDV : Sturcture & Implementation MODULE SIMULATION ORDER 2. Return Visit- all inputs from the module’s instantiations are known Top-Level Local Input/Output Instantiation Dependency SDVSMU Dynamic Verilog Visualization

  15. 2 SDV : Sturcture & Implementation MODULE SIMULATION ORDER 2. Return Visit- all inputs from the module’s instantiations are known 3. Final Return - all Values within the Module are resolved. Top-Level Local Input/Output Instantiation Dependency SDVSMU Dynamic Verilog Visualization

  16. 2 SDV : Sturcture & Implementation MODULE SIMULATION ORDER Top-Level S – Total Simulations/time unit I – Total instantiations within module i Local Input/Output Instantiation Dependency SDVSMU Dynamic Verilog Visualization

  17. 2 SDV : Sturcture & Implementation VARIABLE INTIALIZATION AND EVENT EXTRACTION Dynamically Created Top Level Modules Event Extraction .V Event Monitoring always@ Statements Variable Initialization .V SDVSMU Dynamic Verilog Visualization

  18. 2 SDV : Sturcture & Implementation VARIABLE INTIALIZATION AND EVENT EXTRACTION Dynamically Created Top Level Modules Event Extraction initial begin <assignments> #1 <assignments> end .V t-1 value Variable Initialization t value .V t (event) = t (SDVV) + t (Veriwell) -1 SDVSMU Dynamic Verilog Visualization

  19. 2 SDV : Sturcture & Implementation VARIABLE INTIALIZATION AND EVENT EXTRACTION Event Extraction Static Module Definition Log File Veriwell .V Variable Initialization .log .V Events .V t (event) = t (SDVV) + t (Veriwell) -1 SDVSMU Dynamic Verilog Visualization

  20. OPTIMIZATION Number Of Simulations / time unit Data Structures Searching/Sorting INTERFACE Graphics Enhancement Visualization Configuration Text Editor Error Detection 2 SDV : Extensions SDVSMU Dynamic Verilog Visualization

  21. 2 SDV : Extensions Extension of Verilog HDL for Animation of Dynamically Re-configurable Systems LIBRARY Static Module Definitions DEMO SDVSMU Dynamic Verilog Visualization

  22. 2 SDV SDV Homepagewww.engr.smu.edu/~ralphm/sdvv 2 Ralph Marczynski ralphm@engr.smu.edu Peter-Michael Seidel seidel@engr.smu.edu Marczynski’s Homepagewww.engr.smu.edu/~ralphm THANK YOU SDVSMU Dynamic Verilog Visualization

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