Multiplication and Division

1. Multiplication and Division Our life is frittered away by detail … Simplify, simplify!

2. Use and Distribution Notice • Possession of any of these files implies understanding and agreement to this policy. • The slides are provided for the use of students enrolled in Jeff Six's Computer Architecture class (CMSC 411) at the University of Maryland Baltimore County. They are the creation of Mr. Six and he reserves all rights as to the slides. These slides are not to be modified or redistributed in any way. All of these slides may only be used by students for the purpose of reviewing the material covered in lecture. Any other use, including but not limited to, the modification of any slides or the sale of any slides or material, in whole or in part, is expressly prohibited. • Most of the material in these slides, including the examples, is derived from Computer Organization and Design, Second Edition. Credit is hereby given to the authors of this textbook for much of the content. This content is used here for the purpose of presenting this material in CMSC 411, which uses this textbook.

3. Multiplication • Now that we have explored addition and subtraction (as well as the logical operations), we can visit the more difficult subject of multiplication. • In order to understand how computers do multiplication, we need to revisit basic multiplication (using the good ol’ pencil and paper method learned in elementary school). • Consider this multiplication problem. • The first operand is called the multiplicand. • The second operand is called the multiplier. • The result is called the product. 1000 X 1001 ------- product

4. Multiplication: Step-by-Step • We can do this problem the same way looking at the numbers are decimal or binary… • We simply take the digits of the multiplier one at a time from right to left,multiplying the multiplicand by the single digit of the multiplier and shifting the intermediate product one digit to the left of the earlier intermediate product. • Since computers only deal with binary • numbers, we can only encounter zeros and • ones in the multiplication problem. • With this observation, each step is easy… • Place a copy of the multiplicand in the • proper place if the multiplier digit is a one • OR • Place a zero in the proper place if the • multiplier digit is a zero 1000 X 1001 ----------- 1000 0000 0000 1000 ----------- 1001000

5. Assumptions and Observations • To see how multiplication hardware works, we need to make a few basic assumptions and observations. • We will deal with positive numbers only for now. • Unlike addition and subtraction, performing multiplication with 32-bit numbers can lead to results that are much larger than 32-bits (up to 64-bits actually)…we need to deal with that.

6. S t a r t M u l t i p l i e r 0 = 1 M u l t i p l i e r 0 = 0 1 . T e s t M u l t i p l i e r 0 1 a . A d d m u l t i p l i c a n d t o p r o d u c t a n d p l a c e t h e r e s u l t i n P r o d u c t r e g i s t e r M u l t i p l i c a n d S h i f t l e f t 6 4 b i t s 2 . S h i f t t h e M u l t i p l i c a n d r e g i s t e r l e f t 1 b i t M u l t i p l i e r 6 4 - b i t A L U S h i f t r i g h t 3 2 b i t s 3 . S h i f t t h e M u l t i p l i e r r e g i s t e r r i g h t 1 b i t P r o d u c t C o n t r o l t e s t W r i t e 6 4 b i t s N o : < 3 2 r e p e t i t i o n s 3 2 n d r e p e t i t i o n ? Y e s : 3 2 r e p e t i t i o n s D o n e Multiplication Hardware: Rev 1 • Let’s implement our basic algorithm in hardware…

7. Making This Design Better • This hardware and algorithm works. • However, it has a number of limitations… • We have to store the multiplicand in a 64-bit shift register and half of those bits are always zero. • This means that our 64-bit ALU is overkill. • This happens because we shift the multiplicand to the left, filling in with zeros. • What happens if instead of shifting the multiplicand to the left, we shift the product to the right? • Most of the hardware stays the same – but we only need a 32-bit ALU and a 32-bit multiplicand shift register.

8. S t a r t M u l t i p l i e r 0 = 1 M u l t i p l i e r 0 = 0 1 . T e s t M u l t i p l i e r 0 M u l t i p l i c a n d 3 2 b i t s 1 a . A d d m u l t i p l i c a n d t o t h e l e f t h a l f o f M u l t i p l i e r t h e p r o d u c t a n d p l a c e t h e r e s u l t i n 3 2 - b i t A L U S h i f t r i g h t t h e l e f t h a l f o f t h e P r o d u c t r e g i s t e r 3 2 b i t s S h i f t r i g h t P r o d u c t C o n t r o l t e s t W r i t e 6 4 b i t s 2 . S h i f t t h e P r o d u c t r e g i s t e r r i g h t 1 b i t 3 . S h i f t t h e M u l t i p l i e r r e g i s t e r r i g h t 1 b i t N o : < 3 2 r e p e t i t i o n s 3 2 n d r e p e t i t i o n ? Y e s : 3 2 r e p e t i t i o n s D o n e Multiplication Hardware: Rev 2

9. One More Step to a Better Set of Multiplication Hardware • One more observation can be made upon examination of this hardware… • The wasted space in the product (remember we fill in the left side and shift) is exactly equal to the size of the multiplier. • As the wasted space in the product disappears (as we shift to the right), so do the bits of the multiplier. • Based on this observation, we can combine the right side of the product with the multiplier. We look at the rightmost bit of the 64-bit product/multiplier register as the control test bit.

10. M u l t i p l i c a n d 3 2 b i t s 3 2 - b i t A L U C o n t r o l S h i f t r i g h t P r o d u c t t e s t W r i t e 6 4 b i t s Multiplication Hardware: Rev 3 • Here is the final revision of • our multiplication hardware.

11. Multiplication Hardware: Rev 3 • Multiplication Hardware Usage Summary… • We start with the multiplicand in the multiplicand register. This never changes. • We start with the multiplier in the right half of the product register. This will shift right as we run through the algorithm. • The product slowly shifts right. As a bit crosses the midpoint, it is no longer affected by the algorithm and is final. • The final product is computed when the first final bit reaches the rightmost bit position of the product register. The 64-bit product will then be available in the product register.

12. Multiplication Hardware: Rev 3 –A Simplified Example • Here is an example of the multiplication algorithm, using a 4-bit word (the same algorithm applies for 32-bit words)…

13. Multiplication in MIPS • The MIPS architecture has two special purpose registers, designed to hold the 64-bit product, Hi and Lo. • Multiplication is handled using the multiply (mult) and multiply unsigned (multu) instructions. • The product is retrieved using the move from lo (mflo) instruction. • The high order 32 bits can be retrieved using the move from high (mfhi) instruction… • If multu was used, hi should be zero, otherwise overflow has occurred. • If mult was used, hi must be the extended sign bit of lo, otherwise overflow has occurred. Note that no exceptions are generated on multiplication overflow.

14. Division quotient • On to division… • Let’s go back to elementary school again and perform good ol’ long division… divisor 1001 --------- 1000 | 1001010 -1000 ---- 10 101 1010 -1000 ---- 10 dividend remainder

15. Division Algorithm • Just like multiplication, we have a simple step-by-step algorithm… • See how big of a number can be subtracted, created a digit of the quotient on each attempt. • Binary makes this easy – the number goes in either zero or one time. • This algorithm is simple to implement in hardware. Like multiplication, will implement this algorithm in its basic form and them optimize it. • We will assume positive, unsigned, numbers. • Since we are using a 32-bit word machine, the dividend is 64-bits and the divisor, quotient, and remainder are 32-bits.

16. S t a r t 1 . S u b t r a c t t h e D i v i s o r r e g i s t e r f r o m t h e R e m a i n d e r r e g i s t e r a n d p l a c e t h e r e s u l t i n t h e R e m a i n d e r r e g i s t e r > R e m a i n d e r 0 R e m a i n d e r < 0 – T e s t R e m a i n d e r 2 a . S h i f t t h e Q u o t i e n t r e g i s t e r t o t h e l e f t , 2 b . R e s t o r e t h e o r i g i n a l v a l u e b y a d d i n g s e t t i n g t h e n e w r i g h t m o s t b i t t o 1 t h e D i v i s o r r e g i s t e r t o t h e R e m a i n d e r r e g i s t e r a n d p l a c e t h e s u m i n t h e R e m a i n d e r r e g i s t e r . A l s o s h i f t t h e Q u o t i e n t r e g i s t e r t o t h e l e f t , s e t t i n g t h e n e w l e a s t s i g n i f i c a n t b i t t o 0 D i v i s o r S h i f t r i g h t 3 . S h i f t t h e D i v i s o r r e g i s t e r r i g h t 1 b i t 6 4 b i t s Q u o t i e n t N o : < 3 3 r e p e t i t i o n s 6 4 - b i t A L U S h i f t l e f t 3 3 r d r e p e t i t i o n ? 3 2 b i t s Y e s : 3 3 r e p e t i t i o n s C o n t r o l R e m a i n d e r t e s t W r i t e 6 4 b i t s D o n e Division Hardware: Rev 1

17. How This All Works • This hardware starts with the quotient register set to zero, the divisor in the left half of its 64-bit register, and the dividend in the remainder register. • We shift the divisor right 1 bit for each step. • At each step, we subtract the divisor and then see if the result is less than zero (to see if it fits zero or one time). If it is positive, we generate a one in the quotient; if negative, we generate a zero in the quotient (and undo the subtraction operation).

18. Making It Better • The divisor, again, always has at least 32 of its bits set to zero. • We can accomplish the same result by shifting the remainder to the left instead of shifting the divisor to the right (much like we did for multiplication). • We can almost make things better by realizing that the first step of the current algorithm cannot produce a one in the quotient bit. • If a one were to be produced, the quotient would be too large to fit in the quotient register – this is another result of using fixed-size registers to perform arithmetic operations (we have fixed-size storage capabilities). • By flipping the order of the shift and subtract operations, we can save one iteration (and every divide is quicker!).

19. S t a r t 1 . S h i f t t h e R e m a i n d e r r e g i s t e r l e f t 1 b i t 2 . S u b t r a c t t h e D i v i s o r r e g i s t e r f r o m t h e l e f t h a l f o f t h e R e m a i n d e r r e g i s t e r a n d p l a c e t h e r e s u l t i n t h e l e f t h a l f o f t h e R e m a i n d e r r e g i s t e r > R e m a i n d e r 0 R e m a i n d e r < 0 – T e s t R e m a i n d e r D i v i s o r 3 a . S h i f t t h e R e m a i n d e r r e g i s t e r t o t h e 3 b . R e s t o r e t h e o r i g i n a l v a l u e b y a d d i n g l e f t , s e t t i n g t h e n e w r i g h t m o s t b i t t o 1 t h e D i v i s o r r e g i s t e r t o t h e l e f t h a l f o f t h e 3 2 b i t s R e m a i n d e r r e g i s t e r a n d p l a c e t h e s u m i n t h e l e f t h a l f o f t h e R e m a i n d e r r e g i s t e r . A l s o s h i f t t h e R e m a i n d e r r e g i s t e r t o t h e l e f t , s e t t i n g t h e n e w r i g h t m o s t b i t t o 0 Q u o t i e n t 3 2 - b i t A L U S h i f t l e f t 3 2 b i t s N o : < 3 2 r e p e t i t i o n s 3 2 n d r e p e t i t i o n ? C o n t r o l S h i f t l e f t R e m a i n d e r t e s t W r i t e Y e s : 3 2 r e p e t i t i o n s 6 4 b i t s D o n e . S h i f t l e f t h a l f o f R e m a i n d e r r i g h t 1 b i t Division Hardware: Rev 2

20. One More Improvement • The quotient register can be eliminated. • We can shift the bits of the quotient into the remainder register instead of shifting in zeros as we have been doing. • Remember we flipped the order of shifting and subtraction; this and the new design result in one little problem – the remainder will be shifted left one too many times (so we just shift the remainder - the left half of that shared register - back to the right as a final step).

21. S t a r t 1 . S h i f t t h e R e m a i n d e r r e g i s t e r l e f t 1 b i t 2 . S u b t r a c t t h e D i v i s o r r e g i s t e r f r o m t h e l e f t h a l f o f t h e R e m a i n d e r r e g i s t e r a n d p l a c e t h e r e s u l t i n t h e l e f t h a l f o f t h e R e m a i n d e r r e g i s t e r > R e m a i n d e r 0 R e m a i n d e r < 0 – T e s t R e m a i n d e r 3 a . S h i f t t h e R e m a i n d e r r e g i s t e r t o t h e 3 b . R e s t o r e t h e o r i g i n a l v a l u e b y a d d i n g l e f t , s e t t i n g t h e n e w r i g h t m o s t b i t t o 1 t h e D i v i s o r r e g i s t e r t o t h e l e f t h a l f o f t h e R e m a i n d e r r e g i s t e r a n d p l a c e t h e s u m i n t h e l e f t h a l f o f t h e R e m a i n d e r r e g i s t e r . A l s o s h i f t t h e R e m a i n d e r r e g i s t e r t o t h e D i v i s o r l e f t , s e t t i n g t h e n e w r i g h t m o s t b i t t o 0 3 2 b i t s 3 2 - b i t A L U N o : < 3 2 r e p e t i t i o n s 3 2 n d r e p e t i t i o n ? S h i f t r i g h t Y e s : 3 2 r e p e t i t i o n s C o n t r o l R e m a i n d e r S h i f t l e f t t e s t W r i t e D o n e . S h i f t l e f t h a l f o f R e m a i n d e r r i g h t 1 b i t 6 4 b i t s Division Hardware: Rev 3

22. Division Hardware: Rev 3 • Division Hardware Usage Summary… • We start with the divisor in the divisor register. This never changes. • We start with the dividend in the 64-bit quotient register. This will shift left as we run through the algorithm. • The quotient slowly shifts left. As a bit shifts in, it is no longer affected by the algorithm and is final – the result is built by shifting the appropriate bits in. • The final quotient is computed after 32 bits are shifted in. The 32-bit quotient will then be available in the right half of the quotient register and the 32-bit remainder will be available in the left half of that register.

23. Division Hardware: Rev 3 –A Simplified Example • Here is an example of the division algorithm, using a 4-bit word (the same algorithm applies for 32-bit words)…

24. Division in MIPS • Looking at the hardware required for multiplication and division leads to an obvious observation – the same hardware can be used for both. • All that is needed is a 64-bit register that can shift left and right and a 32-bit ALU that can do addition and subtraction. • The division instructions are divide (div) and divide unsigned (divu). • The Hi and Lo registers are used for the result. • Exceptions are not generated for overflow – or division by zero. Software must check for these conditions.