High Efficiency Amplifiers for EDGE Applications Based on Enhancement-Mode Junction PHEMT

1. High Efficiency Amplifiers for EDGE Applications Based on Enhancement-Mode Junction PHEMT J.C. Clifton, L.Albasha Sony Semiconductor & Electronic Solutions M.Willer Sony CSBD 13th September 2004

2. Id, Ig Id Vth Ig Vg Schottky HEMT Vf = 0.7 (V) Technology: Sony J-PHEMT • Higher forward voltage enables positive drive. JPHEMT Structure Id Source p-Gate Drain InGaAs Channel Ig GaAs Sub. JPHEMT　Vf = 1.2 (V) pn Junction Gate 　　→ High Vf →　High Drain Current

3. Objectives: Designing an EDGE PA • EDGE functionality required from iteration of current GSM PA: Dualmode PA. • Interface to a Direct Modulation Transceiver: to allow future inclusion of WCDMA for future single GSM/EDGE/WCDMA TX Architecture. • Inclusion of EDGE functionality with only a small impact to the size and cost of the basic GSM solution. • Meet EVM specifications over VSWR of 3:1 without isolator and avoid complex calibration/set-up. • Target EDGE efficiencies 25%+ whilst maintaining current GSM performance of 55-60%.

4. LogAmplifier Sin(wt) Phase detector Types of EDGE (8PSK) Power Amplifier Linear/Backed-Off PA Approach • J-PHEMT gives respectable efficiency at several dB back-off whilst maintaining EVM & ACPR • Simple and robust architecture • Also suited for WCDMA • Sometimes issues meeting EVM spec under mismatch conditions: Isolator. • Efficiency suffers under back-off Fixed Vdd=3.5V Operation GSM/EDGE PA Pout=28.5dBm PA Backed off Input Power, Pin Coupler for PACL Increased Vgg for linear operation Polar Loop Approach • J-PHEMT gives good saturated efficiency • Additional efficiency comes at the expense of much greater complexity • Difficult to adopt for WCDMA and use with direct modulator transceiver • Headline efficiency impacted by consumption within AM-AM and AM-PM feedback loops Log Amplifier Amplitude Modulator Phase Modulator or VCO S(t) S(t) PA PA VCO Limiter Limiter Sin(wt) Limiter Phase detector

5. Simulation Test Bench • 3 Stage PA model based on Agilent Eesof model on ADS. • System simulation tool ptolemy to allow inclusion of AM and PM correction loops. Simulation of ACPR, EVM, output power and efficiency. • Used to simulate Linear/Back-off PA in addition to various different types of saturated PA.

6. Saturated PA Architectures Envelope Elimination and Restoration (EER) Power Amplifiers for EDGE Advantage: Drive Level and Power Control (eg drain regulation) similar to GMSK (constant Envelope) Issue: Method of Envelope insertion and correction Corrected Envelope inserted onto drain or gate supply

7. 20mm E-pHEMT Pin=15dBm 20 18 16 14 12 10 EVM% EVM % 8 6 4 2 0 0 0.5 1 1.5 Gate Bias V Control Characteristics (1mm, 900MHz) Drain Gate

8. EER Based on Drain Voltage Corrected RF Output Signal Corrected Drain Voltage (max=3.5V) Associated Drain Current DRAIN VOLTAGE/CURRENT CHARACTERISTICS Loop Dynamics optimised to minimise Error Voltage whilst ensuring loop stability over range of control and supply voltages RF Output Signal make to track EDGE Envelope by AM Correction Loop PAE: 40-45% using fast DC-DC converter

9. LogAmplifier Phase Distortions 60° Phase variation over envelope EVM> 11%. AM-PM Correction loop required to reduce EVM to 1.5% and bring ACPR inside specification: Log Amplifier Amplitude Modulator Phase Modulator or VCO S(t) PA PA VCO Limiter Limiter Sin(wt) Limiter Phase detector

10. EER Based on Gate Voltage Phase error significantly reduced. Resulting EVM of 3.2%. Further reduced with the addition of simple pre-distortion circuit. Simulated PAE of 44%. 20 Degrees

11. Adaptive Bias Control Based on Gate Voltage PA operated in saturated mode. Gate tracking circuit designed to exhibit constant gain over input envelope. Simulated efficiency of 50%. Resulting phase variation of <10° over envelope and EVM of 1%. Phase error due to compression is partly offset by impact of phase variation caused by gate bias shifts required to keep gain constant

12. Practical Measurements of Gate Correction Circuit with Class A/B PA out of Compression Gate AM correction circuit reduced EVM from 16% down to 3%. -36.1dBc, 400KHz offset -54.3dBc, 400KHz offset Implementation Issues for PA in compression: AM Correction loop design –extreme sensitivity of gate voltage to EVM and ACPR.

13. Linear PA Investigations Required improvements for product: • Elimination of output isolator: meet EVM spec in 3:1 Antenna VSWR • Elimination of output coupler/detector and control feedback loops: Open Loop Control • Avoidance of 30-40dB VGA/VVA which impacts power consumption, size and RX Noise performance (TX SAW not acceptable) • Improve efficiency compared to conventional EDGE Linear Power Amps

14. Objectives Met with Modified Linear PAModifications compared to conventional Linear PA to Improve Efficiency at back-off and simplify power control scheme

15. Gate Supply= V1 for GSM V2 for EDGE (V2>V1) DualMode PA GMSK: Compressed EDGE: Linear RFin GMSK O/P Matched Input Step Attenuation: EDGE HI, GMSK LO Vramp (GSM & EDGE) Vd supply=Vbattery Modified Linear PA: Measured Performance RFout 34.5dBm GMSK 28.5dBm EDGE (excluding VGA consumption required for conventional PA)

16. Modified Linear PA Measured Pout/Temperature Characteristics

17. Open-Loop Operation and Mismatch: Measurements Without isolator Temperature stable, variable gain PA Power Error Budget Frequency Variation < +/-1.0dB Temperature Variation < +/-1.0dB WORST CASE < +/-2.0dB SPEC(E2) +/-4.0dB RX Noise: -82.3dBm/100KHz @20Mhz offset from carrier (-10dBm input power, 28.3dBm Output)

18. Conclusions • Promising simulation results for JPHEMT PA in both Saturated (Polar Loop/EER) and Linear modes, proving capabilities of the device. • Adaptive Bias Control of Compressed PA based on gate envelope tracking looks promising from viewpoint of reduced complexity and performance. However, significant implementation issues exist. • Approach based upon modified linear PA proved best suited to meeting original objectives. • EDGE RF functionality possible with very small size/cost impact to GSM solution. Forward compatibility with WCDMA.

19. Acknowledgements • Colleagues at Atsugi Technology Centre: H. Kawasaki, H. Kawamura and H. Motoyama • Support from Thomas LeToux, project student from ULP France/UCL UK. • Agilent ADS UK team for simulation support.