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4. TTL

Vcc. Vcc. R. R. R. IN1 IN2 OUT L L L L H L H L L H H H. IN1 IN2 OUT L L H L H H H L H H H L. IN1. IN1. OUT. IN2. IN2. Vi. OUT. 4. TTL. = Transistor-Transistor Logic. Uses bipolar transistors and diodes. Diode Logic AND gate.

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4. TTL

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  1. Vcc Vcc R R R IN1 IN2 OUT L L L L H L H L L H H H IN1 IN2 OUT L L H L H H H L H H H L IN1 IN1 OUT IN2 IN2 Vi OUT 4. TTL = Transistor-Transistor Logic. Uses bipolar transistors and diodes Diode Logic AND gate Problem… defined levels change easily when loaded. E.g. when diode gates are cascaded. Need for transistor buffering NAND gate!

  2. Dynamic resistance: lower ON (L) voltage, faster switching Limits current in transition Diode AND gate Totem Pole Output TTL: practical realisation Schottky Diodes Clamp diodes

  3. TTL Logic families and specs • Vcc=5V±10%, Vohmin=2.7V, Vihmin=2.0V, Volmax=0.5V, Vilmax=0.8V •  NMh = 0.7V, NML=0.3V • Families: TTL e.g. 7404, 74H04, 74L04 original family • Schottky e.g. 74S04: faster, hi power consumption • Low Power Schottky e.g. 74LS04: lower Pd, Slower Schottky (common) • Advanced Schottky e.g. 74AS04 2x speed of S, same Pd • Adv. Low Pwr Sky e.g. 74ALS04 • see table 3-11, Wakerly • For LS, typically: IILmax=-0.4mA, IIHmax=20uA, IOLmax=8mA, IOHmax=-400uA. • FANOUT (LSTTL into LSTTL)=20 • NB: TTL outputs can sink more current than they can source.

  4. TTL vs CMOS

  5. VOHMIN, VOLMAX VOHMIN, VOLMAX VIHMIN, VILMAX VIHMIN, VILMAX 4.9 3.5 2.0 2.7 1.5 0.5 0.8 0.1 CMOS TTL TTL CMOS Applications: CMOS/TTL interfacing    

  6. 5. Applications: Unused inputs Floating inputs can lead to unreliable operation!!! Unused (Floating) Inputs [] Tie together and bundle with used inputs OR [] Tie HIGH thru pull up resitor, Rpu OR [] Tie LOW thru pull down resistor, Rpd [] For CMOS use 1K-10K values [] For TTL calculate based on # of inputs tied thru resistor so that: Vcc-RpuIIHmax > VIHmin RpdIILmax < VILmax []Too small Rpu makes TTL susceptible to spikes etc. over 5.5V. See Sec 3.10.4, 3.5.6 Wake. Must ensure that does not affect design function. E.g. tie HIGH for AND/NAND or LOW for OR/NOR

  7. Power supply filtering • For each logic IC place a small capacitor (0.01uF tp 0.1uF) across Vcc and ground in close proximity to the IC • Reduces transient effect of switching on power supply, particularly when supply source is connected via long circuit path (resistive and inductive effects). Essentially each capacitor provides a local reservoir for fast supply of charge required when the device switches

  8. Vcc Vcc A B Q1 Q2 Z 0 0 open open 1 0 1 open ON 1 1 0 ON open 1 1 1 ON ON 0 Applications: Open-drain (CMOS) or open collector (TTL) outputs • In CMOS no PMOS transistor, use external pull-up resistor for Vcc drive Calculate external Rpu so that VOLMAX achieved at IOLMAX. Must include other loads so this gives minimum Rpu. Rpu IC Z A Q1 B Q2 Output stage of Open Drain NAND

  9. Why ? • Slightly higher current capability • Can form an open-drain/collector bus. Can select data for access to common bus.. E.g for Dataout = Datai set Enablej =0, jI, Enablei =1, Problem -- really bad rise time due to all O/P capacitances in parallel and large pullup.

  10. Vout EN EN Vin Vout 0 x HiZ 1 1 0 1 0 1 Applications: Bus Access - Contention and Tristate Logic Common bus Best “fix”…. Tristate logic Vin 0 1 a 1 b ?? 0 “regular TTL or CMOS • Get bus contentionwhen two outputs try to drive the bus to different states. • Value on the bus may be indeterminate; • Damage possible (a driving b!!) • On a PC data bus, can cause PC to crash • Available in inverting or non-inverting .. Sec 3.7.3 Wakerly. • NO Pull-up needed • NO degradation in transition speed

  11. Applications: Digital meets analog Schmitt Trigger Inputs…Sec3.7.2/Wakerly • Schmitt trigger devices are used primarily to deal with signal levels which are not at valid logic levels. They can therefore be used for • interfacing noisy analogue signals to a logic circuit e.g. signals from switches, RC networks etc. • interfacing slow signals (i.e. signals which remain in the invalid range for relatively long periods) • regenerating degraded logic signals e.g. signals on a long serial communication line. Schmitt trigger devices do comply with the input thresholds of the respective family. However, they employ a bit of hysterisis (memory!!) to take care of invalid signal levels. The devices are characterised by upper and lower thresholds (UT, LT). When the input exceeds UT it is treated as a logic 1 UNTIL it goes below LT. Then, and only then, is it treated as a logic 0. Vo VT Vi VL VH Schmitt Trigger o/p Characteristic Standard logic o/p Characteristic

  12. Vcc R Logic Device Applications: Logic Drive • ILED is 10mA typically worst case • Use formula: • VOL+VLED+(ILED*R)=VCC • to determine R. • NB……. • Can assume worst case VOL=VOLMAX for some CMOS as well as TTL at IOL=ILED. • Best to use device for which IOLMAX>ILED. Driving a LED with TTL ILED VLED VOL Low output turns LED ON Drive current typ 5 -10mA Use buffers for extra drive

  13. Vcc Free-wheeling diode protects electronics from coil back emf Logic Device Low output turns activates relay or solenoid Applications: Logic Drive • 5V relays do exist. • Some incorporate the free wheeling Diode. • Most have enough internal resistance to operate directly as shown. • Check using LED computation if built in resistance is sufficient or if an external series resitance is needed Driving a Solenoid or relay with TTL

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