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C ISC Design

C ISC Design

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C ISC Design

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  1. CISC Design By Ralph M. Weber Jr. Appendix Page

  2. CISC Design Control Signals Appendix Page

  3. Table 3: Control Signals Appendix Page

  4. CISC Design Flowchart Appendix Page

  5. Figure 5: Flowchart 1 Appendix Page

  6. Figure 6: Flowchart 1a Appendix Page

  7. Figure 7: Flowchart 1b Appendix Page

  8. CISC DesignConsole Appendix Page

  9. Figure 9: CISC Design of Console User Console Start Button 48 LED 32 switches START Load Button 32 SW HALT LED 16 switches LOAD Reset Button ERROR LED 16 SW RESET Appendix Page

  10. Figure 10: Combinational Logic Appendix Page

  11. CISC Design Main CPU Appendix Page

  12. 16 32 16 16 16 16 32 32 32 16 16 16 32 32 32 16 32 Figure 12: Design of Main Computer Main Computer Data Paths MDR(OP) IR CU MM SW MDR PC MDR SW ACO MDR(ADR) MAR ACC XR ACC=0 ACC>=0 XR=0 ACO ALU MDR(ADR) RD WR ER Appendix Page

  13. Figure 13: Design of Main Computer Main Computer Control Signals IR CU Cn C3, C11 MDR MM C4 . PC . . C0 C2,C10 C0, C5, C6 C12, C13, C21, C22 MAR C7, C8, C9, C14, C15, C16, C17, C18, C19, C20 ACC XR ALU C7, C8, C18, C19, C20 C1 C2 RD WR Appendix Page

  14. Figure 14: CISC Design of MDR MDR D(0) … D(15) O(0) … O(7) … X I 0 … 31 X I O(0) O(1) O(2) O(3) O(4) O(5) O(6) O(7) D(0) D(1) D(2) D(3) D(4) D(5) D(6) D(7) D(8) D(9) D(10) D(11) D(12) D(13) D(14) D(15) Appendix Page

  15. Figure 15: MDR Detail Design Appendix Page

  16. Figure 16:CISC Design of Opcode(s) O(7) O(6) O(5) O(4) O(3) O(2) O(1) O(0) Appendix Page

  17. Figure 17: CISC Design MAR & PC MAR A(0) … A(n) 0 … 15 A(0) A(1) A(2) A(3) A(4) A(5) A(6) A(7) A(8) A(9) A(10) A(11) A(12) A(13) A(14) A(15) PC P(0) … P(n) 0 … 15 P(0) P(1) P(2) P(3) P(4) P(5) P(6) P(7) P(8) P(9) P(10) P(11) P(12) P(13) P(14) P(15) Appendix Page

  18. Figure 18: MAR Detail Design Appendix Page

  19. Figure 19: PC Detail Design Appendix Page

  20. Figure 20: CISC Design of XR & ACC XR R(0) … R(n) 0 15 ACC H(0) … H(n) 0 31 Appendix Page

  21. Figure 21: XR (i=0) Detail Design Appendix Page

  22. Figure 22: XR (i=30) Detail Design Appendix Page

  23. Figure 23: XR (i=31) Detail Design Appendix Page

  24. Figure 24: ACC (i=0) Detail Design Appendix Page

  25. Figure 25: ACC (i=30) Detail Design Appendix Page

  26. Figure 26: ACC (i=31) Detail Design Appendix Page

  27. Figure 27: CISC Design of IR I(0) … I(n) 0 … 15 I(0) I(1) I(2) I(3) I(4) I(5) I(6) I(7) IR I(8) I(9) I(10) I(11) I(12) I(13) I(14) I(15) Appendix Page

  28. Figure 28: IR Detail Design Appendix Page

  29. Figure 29: ALU Detail Design Appendix Page

  30. Table 30: ALU Tables Appendix Page

  31. CISC Design Input Equations See text in body of report Appendix Page

  32. CISC Design Micro Control Unit Appendix Page

  33. 32 9 Cn 16 16 16 Figure 33: Design of Micro Control Unit Micro Control Unit (Data Flow) EEPROM mMDR mMDR IR mPC Control Signal for CPU RD Appendix Page

  34. Figure 34: Design of Micro Control Unit Micro Control Unit (Control signals) EEPROM CLK mMDR CLK mPC START CLK RD Appendix Page

  35. Figure 35: CISC Design of EEPROM EEPROM GO to LOAD Indirection Table GO to … GO to … GO to HALT FETCH Micro Instruction ( Fetch & Execute) LOAD … HALT Appendix Page

  36. Figure 36: CISC Design mPC mPC p(0) … p(n) 0 … 8 Appendix Page

  37. Figure 37: mPC Detail Design Appendix Page

  38. Figure 38: CISC Design mMDR mMDR m(0) … m(n) 0 … 31 Appendix Page

  39. Figure 39: mMDR Detail Design Appendix Page

  40. Figure 40: CISC Design of Control Unit mMDR (External) Control Unit I/E C(30) … C(0) 31 … 0 Appendix Page

  41. Table 41: External InstructionsSee next page Appendix Page

  42. Figure 42: CISC Design of Control Unit mMDR (Internal) Control Unit I/E o(7) … o(0) Not used a(8) … a(0) 31 … 0 Appendix Page

  43. Table 43: Internal InstructionsSee next page Appendix Page

  44. CISC Design User Program See next page Appendix Page