Handout # 1: Course Logistics and Introduction

1. Handout # 1:Course Logistics and Introduction CSC 2203 – Packet Switch and Network Architectures Professor Yashar Ganjali Department of Computer Science University of Toronto yganjali@cs.toronto.edu http://www.cs.toronto.edu/~yganjali

2. Today • Outline • What this course is about • Logistics • Course structure, assignments, evaluation • What is expected from you • What you want to know • Overview • Packet switching systems • Topics and problems studied in this course University of Toronto – Fall 2012

3. Outline • Graduate level course • Packet switching systems • Internet routers, Ethernet switches • Architectures • Related problems • This year: software defined networks • Theory + Practice • Switching systems are simple enough for us to prove something about them • Yet they are complex enough to work in practice University of Toronto – Fall 2012

4. Outline – Part I • Introduction • What is a packet switch system? • Evolution of the Internet, and Internet routers • Basic architectural components • Some example architectures University of Toronto – Fall 2012

5. Outline – Part II • Software defined networks • Innovation in computer networks • Control vs. data plane • Challenges and promises University of Toronto – Fall 2012

6. Outline – Part III • Output Queued Switches • Emphasis on deterministic analysis • OQ as the simplest and ideal architecture • Output queueing and shared-memory switches • Packet arrival processes: (s, r)-constrained arrivals, leaky buckets, Bernoulli arrivals, bursty arrivals, adversaries • Providing bandwidth and delay guarantees, scheduling, fairness, Fair-Queueing, Generalized Processor Sharing and Deficit Round Robin. • Practicaldifficulties: • When output queued switches are impractical; • Memory bandwidth and capacity scaling • Some approaches: Emulating output queued switches. Parallel packet buffers as standalone shared memory, with design examples. • Routers with a single stage of buffering and constraint sets, Parallel Shared Memory Routers, Distributed Shared Memory Routers, and Parallel Packet Switches. • Output link scheduling in a Distributed Shared Memory router. Combined input and output queued (CIOQ) switches, stable marriage matchings. University of Toronto – Fall 2012

7. Outline – Part IV • Input Queued Switches • Emphasis on probabilistic analysis • Definition of IQ switch with single FCFS queue • Switching fabrics, crossbars • Head of line blocking; the balls and bins model • Virtual output queues and crossbar schedulers • Bipartite Matchings: Maximum Sized Matchings, Maximum Weight Matchings, maximal matchings • Definitions of 100% throughput • Lyapunov functions • When traffic is uniform: simple RR and random matchings. • When traffic matrix is known: Birkhoff von Neuman decomposition. When traffic is not known: heuristics. PIM, iSLIP, WFA University of Toronto – Fall 2012

8. Outline – Part V • Other Switch Architectures • Buffered crossbars • Multistage switches • Clos networks • 2-stage switches: randomized, deterministic • Miscellaneous Interesting Problems • Software-defined networks • Address lookup: exact matches, longest prefix matches, performance metrics, hardware and software solutions • Cells switching versus packets switching • Buffer sizing • Small buffers • Tiny buffers • Packet classification University of Toronto – Fall 2012

9. Outline – Fundamental Tools • Fundamentals • Introduction to probability • Poisson process • Discrete and Continuous-time Markov chains • Basic queueing theory: • M/M/1 • M/G/1 • Little’s result • PASTA University of Toronto – Fall 2012

10. Logistics • Office hours • Tue. 3-4 PM, Wed. 3-4 PM, BA5238 • Or by appointment • Course web page • http://www.cs.toronto.edu/~yganjali/courses/csc2203/ • Please check regularly for announcements. • Class mailing list • csc2203-psana@cs.toronto.edu • Send me an e-mail to be added to the list. • Any (course-related!) question posted to the list will be answered within 48 hours. University of Toronto – Fall 2012

11. Logistics • Prerequisites • Any introductory course on networking • Algorithms • Basic probability theory • Papers • URLs will be provided on class web page • Please read suggested papers BEFORE class University of Toronto – Fall 2012

12. Logistics • Grading • Class participation, notes, and discussions: 10% • Paper presentation: 30% • Final project: 60% • Proposal: 5% - 1-2 pages • Intermediate report: 10% - 3 pages • Presentation: 15% - Last week of classes • Final report: 30% - 6 pages • Deadlines • 5% mark deduction for each day of delay, up to 4 days. • Exception: final report deadline is hard. University of Toronto – Fall 2012

13. Logistics • Final Project • Groups of two students • Project topic • Choose from the offered list; or • Talk to me and define your own University of Toronto – Fall 2012

14. Logistics • Academic Integrity • Projects • Avoid plagiarism. I’m interested in what YOU think. • Please read • “Guideline for avoiding plagiarism” http://www.cs.toronto.edu/~fpitt/documents/plagiarism.html • “Advice about academic offenses” http://www.cs.toronto.edu/~clarke/acoffences/ University of Toronto – Fall 2012

15. Logistics • Accessibility Needs • The University of Toronto is committed to accessibility. If you require accommodations or have any accessibility concerns, please visit http://studentlife.utoronto.ca/accessibility as soon as possible. University of Toronto – Fall 2012

16. Acknowledgements • Special thanks to: • Prof. Nick McKeown; and • Prof. BalajiPrabhakar University of Toronto – Fall 2012

17. Questions? What else do you like to know about this course? University of Toronto – Fall 2012

18. Introduction • Background • What is a router? • Why do we need faster routers? • Why are they hard to build? • Architectures and techniques • The evolution of router architecture • IP address lookup • Packet buffering • Switching University of Toronto – Fall 2012

19. D R3 R1 R4 D A B E R2 C R5 Destination Next Hop F D R3 E R3 F R5 What is Routing? University of Toronto – Fall 2012

20. R3 R1 R4 D A 1 4 16 32 D Ver HLen T.Service Total Packet Length Fragment ID Flags Fragment Offset B E TTL Protocol Header Checksum 20 bytes Source Address R2 C R5 Destination Address Destination Next Hop F D R3 Options (if any) E R3 Data F R5 What is Routing? University of Toronto – Fall 2012

21. R3 R1 R4 D A B E R2 C R5 F What is Routing? University of Toronto – Fall 2012

22. POP3 POP2 POP1 D POP4 A B E POP5 POP6 C POP7 POP8 F Points of Presence (POPs) University of Toronto – Fall 2012

23. Where High Performance Routers are Used (2.5 Gb/s) R2 (2.5 Gb/s) R1 R6 R5 R4 R7 R3 R9 R10 R8 R11 R12 R14 R13 R16 R15 (2.5 Gb/s) (2.5 Gb/s) University of Toronto – Fall 2012

24. What a Router Looks Like Cisco GSR 12416 Juniper M160 19” 19” Capacity: 160Gb/sPower: 4.2kW Capacity: 80Gb/sPower: 2.6kW 6ft 3ft 2ft 2.5ft University of Toronto – Fall 2012

25. Basic Architectural Components of an IP Router Routing Protocols Routing Table Control Plane Data-path per-packet processing Forwarding Table Switching University of Toronto – Fall 2012

26. Per-packet Processing in an IP Router 1. Accept packet arriving on an incoming link. 2. Lookup packet destination address in the forwarding table, to identify outgoing port(s). 3. Manipulate packet header: e.g., decrement TTL, update header checksum. 4. Send packet to the outgoing port(s). 5. Buffer packet in the queue. 6. Transmit packet onto outgoing link. University of Toronto – Fall 2012

27. Data Hdr Data Hdr IP Address Next Hop Address Table Buffer Memory Generic Router Architecture Header Processing Lookup IP Address Update Header Queue Packet ~1M prefixes Off-chip DRAM ~1M packets Off-chip DRAM University of Toronto – Fall 2012

28. Data Data Data Hdr Hdr Hdr Header Processing Header Processing Header Processing Lookup IP Address Lookup IP Address Lookup IP Address Update Header Update Header Update Header Address Table Address Table Address Table Data Data Hdr Hdr Data Hdr Generic Router Architecture Buffer Manager Buffer Memory Buffer Manager Buffer Memory Buffer Manager Buffer Memory University of Toronto – Fall 2012

29. Why do we Need Faster Routers? • To prevent routers becoming the bottleneck in the Internet. • To increase POP capacity, and to reduce cost, size and power. University of Toronto – Fall 2012

30. Why we Need Faster Routers 1: To prevent routers from being the bottleneck Packet processing Power Link Speed 10000 1000 2x / 18 months 2x / 7 months 100 Fiber Capacity (Gb/s) 10 1 1985 1990 1995 2000 0,1 TDM DWDM Source: SPEC95Int & David Miller, Stanford. University of Toronto – Fall 2012

31. POP with smaller routers Why we Need Faster Routers 2: To reduce cost, power & complexity of POPs POP with large routers • Ports: Price >$100k, Power > 400W. • It is common for 50-60% of ports to be for interconnection. University of Toronto – Fall 2012

32. Why are Fast Routers Difficult to Make? It’s hard to keep up with Moore’s Law: • The bottleneck is memory speed. • Memory speed is not keeping up with Moore’s Law. University of Toronto – Fall 2012

33. 1.1x / 18 months Moore’s Law 2x / 18 months Why are Fast Routers Difficult to Make?Speed of Commercial DRAM It’s hard to keep up with Moore’s Law: • The bottleneck is memory speed. • Memory speed is not keeping up with Moore’s Law. University of Toronto – Fall 2012

34. Why are Fast Routers Difficult to Make? • It’s hard to keep up with Moore’s Law: • The bottleneck is memory speed. • Memory speed is not keeping up with Moore’s Law. • Moore’s Law is too slow: • Routers need to improve faster than Moore’s Law. University of Toronto – Fall 2012

35. Router Performance Exceeds Moore’s Law • Growth in capacity of commercial routers: • Capacity 1992 ~ 2Gb/s • Capacity 1995 ~ 10Gb/s • Capacity 1998 ~ 40Gb/s • Capacity 2001 ~ 160Gb/s • Capacity 2003 ~ 640Gb/s • Capacity 2007 ~ 4Tb/s • Capacity 2010 ~ 16Tb/s Average growth rate: 2x / 18 months. University of Toronto – Fall 2012

36. Outline • Background • What is a router? • Why do we need faster routers? • Why are they hard to build? • Architectures and techniques • The evolution of router architecture. • IP address lookup. • Packet buffering. • Switching. University of Toronto – Fall 2012

37. CPU Buffer Memory Route Table CPU Line Interface Line Interface Line Interface Memory MAC MAC MAC Typically <0.5Gb/s aggregate capacity First Generation Routers Shared Backplane Line Interface University of Toronto – Fall 2012

38. Fwding Cache Second Generation Routers CPU Buffer Memory Route Table Line Card Line Card Line Card Buffer Memory Buffer Memory Buffer Memory Fwding Cache Fwding Cache MAC MAC MAC Typically <5Gb/s aggregate capacity University of Toronto – Fall 2012

39. Fwding Table Third Generation Routers Switched Backplane Line Card CPU Card Line Card Local Buffer Memory Local Buffer Memory CPU Line Interface Routing Table Memory Fwding Table MAC MAC Typically <50Gb/s aggregate capacity University of Toronto – Fall 2012

40. Fourth Generation Routers/SwitchesOptics inside a router for the first time Optical links 100s of metres Switch Core Linecards 0.3 - 10Tb/s routers in development University of Toronto – Fall 2012

41. Software Defined Networks Control Plane Control Plane Control Plane Control Plane Data Plane Data Plane Data Plane Data Plane University of Toronto – Fall 2012

42. Software Defined Networks – Cont’d Controller OpenFlow Protocol PC SSL OpenFlow Switch Data Plane Data Plane Data Plane Data Plane University of Toronto – Fall 2012

43. Outline • Background • What is a router? • Why do we need faster routers? • Why are they hard to build? • Architectures and techniques • The evolution of router architecture • IP address lookup • Packet buffering • Switching University of Toronto – Fall 2012

44. Header Processing Header Processing Lookup IP Address Lookup IP Address Update Header Update Header Address Table Address Table Lookup IP Address Lookup IP Address Lookup IP Address Address Table Address Table Address Table Generic Router Architecture Buffer Manager Buffer Memory Header Processing Buffer Manager Lookup IP Address Update Header Buffer Memory Address Table Buffer Manager Buffer Memory University of Toronto – Fall 2012

45. IP Address Lookup • Why it’s thought to be hard: • It’s not an exact match: it’s a longest prefix match. • The table is large: about 400,000 entries today, and growing. • The lookup must be fast: about 30ns for a 10Gb/s line. University of Toronto – Fall 2012

46. 128.9.16.14 IP Lookups find Longest Prefixes 128.9.172.0/24 128.9.16.0/21 128.9.172.0/21 142.12.0.0/19 65.0.0.0/8 128.9.0.0/16 0 232-1 Routing lookup:Find the longest matching prefix (aka the most specific route) among all prefixes that match the destination address. University of Toronto – Fall 2012

47. IP Address Lookup • Why it’s thought to be hard: • It’s not an exact match: it’s a longest prefix match. • The table is large: about 400,000 entries today, and growing. • The lookup must be fast: about 30ns for a 10Gb/s line. University of Toronto – Fall 2012

48. Source: http://www.cidr-report.org/ Address Tables are Large University of Toronto – Fall 2012

49. IP Address Lookup • Why it’s thought to be hard: • It’s not an exact match: it’s a longest prefix match. • The table is large: about 400,000 entries today, and growing. • The lookup must be fast: about 30ns for a 10Gb/s line. University of Toronto – Fall 2012

50. Lookups Must be Fast Year Line 40B packets (Mpkt/s) 1997 622Mb/s 1.94 1999 2.5Gb/s 7.81 2001 10Gb/s 31.25 2003 40Gb/s 125 University of Toronto – Fall 2012