Review for Exam 2

1. Review for Exam 2 • Chapters 4 and 5 • Close book and close notes • Bring pencil • No computers or cell phones allowed

3. Implementations: Half-Adder X S Y C = Å S X Y = × C X Y X Y C S 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0 • The most common half adder implementation is:

4. Implementation: Full Adder Ai Bi Gi Pi Ci Ci+1 Si • Full Adder Schematic for bit i with G = generate (=AB) and P = propagate (=AB) Ci+1=Gi+ Pi· Ci or: Co= (G = Generate) OR (P =Propagate AND Ci = Carry In) Si =(AiBi)Ci Co = AB + (AB)Ci or Ci+1 = AiBi + (AiBi )Ci

5. 4-bit Ripple-Carry Binary Adder Ai Bi Ci+1 Ci FA Si • A four-bit Ripple Carry Adder made from four 1-bit Full Adders: • Slow adder: many delays from input to output

6. Delay of a Full Adder Ai Bi Gi Pi = = Å Å Å Å S0 Si Ai A0 Bi B0 Ci C0 Ci 2+2=4 delays = = + + Å Å A0 Ai C1 Ci+1 B0 Bi ( ( Ai A0 Bi B0 ) ) C0 Ci Ci+1 Si @2 2+2=4 delays • Assume that AND, OR gates have 1 gate delay and the XOR has 2 gate delays • Delay of the Sum and Carry bit: 2 delays @3

7. Delay of the Carry Ai Bi Gi = = + + Å Å A2 A1 Pi C2 C3 B2 B1 ( ( A1 A2 B1 B2 ) ) C2 C1 Ci Ci+1 Si @4 @2 @? @? @6 @2 @7 @8 C4 : delay 8+2 = 10 For n stage: delay of Cn: 2n+2 delays! andSn: 2n+4 (=@Cn+ 2) The bottleneck is the delay of the carry.

8. Delay in a Ripple-carry adder Example: 4-bit adder (n=4) @0 @0 @4 @6 @8 @4 @10 @8 @6 @10 One problem with the addition of binary numbers is the length of time to propagate the ripple carry from the least significant bit to the most significant bit. • Example: 32-bit Ripple-carry has a unit gate delay of 1ns. • What is the total delay of the adder? • What is the max frequency at which it can be clocked?

9. Carry Lookahead Adder • Uses a different circuit to calculate the carry out (calculates it ahead), to speed up the overall addition • Requires more complex circuits. • Trade-off: speed vs. area (complexity, cost)

10. PFA generates G and P 4-bit Implementation @6 @6 @4 @6 @4 C1 = G0 + P0 C0 @4 C2= G1 + P1G0 + P1P0 C0 Carry lookahead logic @4 C3= G2 + P2G1 + P2P1G0 + P2P1P0 C0

11. 4-3 b. Complements • Two type of complements: • Diminished Radix Complement of N • Defined as (rn- 1)– N, with n = number of digits or bits • 1’s complement for radix 2 • Radix Complement • Defined as rn - N • 2’s complement in binary • As we will see shortly, subtraction is done by adding the complement of the subtrahend • If the result is negative, takes its 2’s complement

12. Binary 1's Complement • For r = 2, N = 0111 00112, n = 8 (8 digits): (rn– 1) = 256 -1 = 25510 or 111111112 • The 1's complement of 011100112 is then: 11111111 – 01110011 10001100 • Since the 2n – 1 factor consists of all 1's and since 1 – 0 = 1 and 1 – 1 = 0, the one's complement is obtained by complementing each individual bit (bitwise NOT). rn – 1 - N 1’s compl

13. Binary 2's Complement Invert bit-wise 2’s complement • For r = 2, N = 0111 00112, n = 8 (8 digits), we have: (rn ) = 25610 or 1000000002 • The 2's complement of 01110011 is then: 100000000 – 01110011 10001101 • Note the result is the 1's complement plus 1: - N rn 2’s compl 01110011 10001100 + 1 10001101

14. Alternate 2’s Complement Method • Given: an n-bit binary number, beginning at the least significant bit and proceeding upward: • Copy all least significant 0’s • Copy the first 1 • Complement all bits thereafter. • 2’s Complement Example: 10010100 • Copy underlined bits: 100 • and complement bits to the left: 01101100

15. 3-3c. Subtraction with 2’s Complement • For n-digit, unsigned numbers M and N, find M  N in base 2: Algorithm Add the 2's complement of the subtrahend N to the minuend M: M + (2n N) = M  N + 2n

16. Unsigned 2’s Complement Subtraction Example 1 • Find 010101002 – 010000112 01010100 01010100 –01000011 +10111101 00010001 Discard carry 1 84 -67 17 2’s comp The carry of 1 indicates that no correction of the result is required

17. Unsigned 2’s Complement Subtraction Example 2 • Find 010000112 – 010101002 01000011 01000011 – 01010100 + 10101100 11101111 00010001 • The carry of 0 indicates that a correction of the result is required. • Result = – (00010001) 0 67 -84 -17 2’s comp 2’s comp

18. Signed Binary Numbers • So far we focused on the addition and subtraction of unsigned numbers. • For SIGNED numbers: • How to represent a sign (+ or –)? • One need one more bit of information. • Two ways: • Sign + magnitude • Signed-Complements • Thus: • Positive number are unchanged • Negative numbers: use one of the above methods

19. Exercise • Give the sign+magnitude, 1’s complement and 2’s complement of (using minimal required bits): Sign+MagOne’s compl.Two’s compl. +2 010 010 010 - 2 110 101 110 +3 011 011 011 - 3 111 100 101 +0 000 000 000 - 0 100 111 000

20. 2’s Complement Arithmetic • Addition: Simple rule • Represent negative number by its 2’s complement. Then, add the numbers including the sign bits, discarding a carry out of the sign bits (2's complement): • Indeed, e.x. M+(-N) M + (2n-N) • If M ≥ N: (M-N) + 2n ignore carry out: M-N is the answer in two’s complement) • If M ≤ N: (M-N) + 2n = 2n – (N-M) which is 2’s complement of the (negative) number (M-N): -(N-M). • Subtraction:M-N  M + (2n-N) Form the complement of the number you are subtracting and follow the rules for addition.

21. Overflow examples (continued) 1 1 0 0 0 0 0 1 0 0 1 0 +1 1 0 0 0 1 0 0 0 0 1 1 18 - 15 3 3 -31! correct answer no overflow Overflow occurs when the carry-in into the sign bit (most left bit) is different from the carry-out of the sign bit. carries 0 1 1 1 1 0 0 1 0 0 1 0 +0 0 1 1 1 1 1 0 0 0 0 1 18 +15 33 wrong answer due to overflow

23. 5-1 Sequential circuit block diagram • Combinatorial Logic gives: • Next state functionNext State = f(Inputs, State) • Output function CLOCK Outputs Inputs Combina-tional Logic Next State State (or present state) Storage Elements Synchronous machine

24. Types of Sequential Circuits Illustra Mealy Comb. logic Outputs Inputs Combina-tional Logic State (or present state) Next State Storage Elements CLOCK • Moore machine: • Outputs = h(State) • Mealy machine • Outputs = g(Inputs, State)

25. Basic (NOR) S –R Latch R (reset) Q Q S (set) • S R Q Q • 0 0 • 0 1 • 0 • 1 1 0 0 not allowed, unstable (Q=Q) • Function Table: • This element is also the basic building block in SRAM memories hold, no change 0 1 Reset 1 0 Set

26. Timing waveforms of NOR S-R latch S Q 1 tpd unstable Q 2 R not allowed S 0 R 0 set 0 Q 1 reset Q No change

27. Clocked (NOR) S-R Latch S Clk R Q 1 Q 2 • Clk=0: input has no effect: latch is always in “hold” mode • Clk=1: latch is a regular S-R latch

28. Function table of the (NAND) S - R latch S (set) Q Q R (reset) hold, no change 1 0 Set 0 1 Reset 1 1 not allowed, unstable (Q=Q=1) • S = 0, R = 0 is forbidden as input pattern Function table: • S R Q Q • 1 1 • 0 1 • 0 • 0 0

29. Latch with NAND S S Q C S R Next state Q(t+1) C Q R Q R When both S=R=1: the NAND gates act as inverters and the circuit implements two inverters: “hold mode” Q 1 Q Q Q(t) no change • 0 x x • 0 0 • 1 0 1 • 1 1 0 • 1 1 1 Q(t) no change Q(t+1) = 0, Reset 1 Q(t+1) = 1, Set Q=Q’=1 Undefined 1 A = A A A Clocked latch:

30. D Latch (Delay latch) D Q C Q Function table D latch: D Q(t+1) 0 0 1 1 D Q Q C • S-R Latch can be usedfor at D Latch: Q(t+1) SR latch: • S R Q+ Q+ • 0 0 hold, • 0 1 01 • 0 10 • 1 1 0 0

31. Latch issues • Latches can cause serious timing problems (races) in sequential circuits • Due to the fact that a latch is “transparent” when the clock C = 1 • The timing problems can be prevented by using “Flip-Flops”

32. The Latch Timing Problem (continued) X3 • Similar timing problems in the sequential circuits: Outputs Inputs Combina-tional Logic X2 X2 X1 X1 X1 X0 X2 X1 X0 X2 D Latch (storage) Next State State 1 C=0 • The state should change only once every new clock cycle: • C=1: • Now the current state becomes X1 and a new state is generated by the combinational logic circuit: X2. • However, if C=1, the new “next state” X2 will create a new current state X2!, etc…

33. How to solve the timing problem: use Flip-Flops C D Q In Q C Out • A solution to the latch timing problem is to break the closed path from In to Out within the storage element Out In Out In D Q C: 0 1 C: 0 1 Q C D-Flip-Flop D-Latch C In Out

34. Symbol: Master-Slave Flip-Flop Y S S S Q Q Q Q C C C Y’ R R Q R Q Notice; the output changes when the clock C goes low. C Symbol: S C R Q Q Sometimes one adds: To indicate that the input responds when C=1, but the output changes when C goes to 0

35. Flip-Flop Problem: 1’ catching Y S S S Q Q Q Q C C C Y’ R R Q R Q wrong output should have been 0 Glitch C S R Y Master out Q Slave out Slave active Master active 1’ catching

36. Flip-Flop Solution: Edge-triggered Positive edge-triggered Negative edge-triggered Clock ignored In The value of the input at the clock transition (negative or positive) determines the output • An edge-triggered flip-flop changes values at the clock edge (transition): • responds to its input at a well-defined moment (at the clock-transition) • ignores the pulse while it is at a constant level

37. Edge-Triggered D Flip-Flop D D S Q Q Q C C C Q R Q Q • The 1s-catching behavior is not present with D replacing S and R inputs • The change of the D flip-flop output is associated with the negative edge at the end of the pulse: • It is called a negative-edge triggered flip-flop

38. No 1’s catching in the edge-triggered D Flip-Flops D D S Q Q Q C C C Q R Q Q no 1’ catching correct output Y C D Y Master out Q Slave active Slave out Master active

39. Exercise

40. Timing diagram of a (Nor) S-R Master-Slave Flip-Flop S Q Q Q C R Q = Y S S Q C C Slave active Y’ R R Q Master active Master active C S R S C R Q Y undefined Master out Y’ Q undefined Q undefined Slave out

41. Direct inputs: active-low or active-high Direct inputs • S R C D Q Q’ • 0 1 x x 1 0 • 0 x x 0 1 • 1 1 0 0 1 • 1 1 1 1 0 S D Q C Q R • S R C D Q Q’ • 0 1 x x 0 1 • 0 x x 1 0 • 0 0 0 0 1 • 0 0 1 1 0 S D Q C Q R • D flip-flop with active-low direct inputs : • Active high direct inputs:

42. 5-4 Sequential Circuit Analysis • Consider the following circuit: input x A Q D • What does it do? • How do the outputs change when an input arrives? A Q’ C states B Q D CLK Q' C y output

43. Step 1: Input and output equations DA x A Q D A Q’ C Next State DB B Q D CLK Q' C y Output • Boolean equations for the inputs to the flip flops: • DA = A(t)x(t)+B(t)x(t) • DB = A(t)x(t) • Output y • y(t) = x(t)(B(t) + A(t)) Present state

44. State Table Inputs of the table Outputs of the table Present State Input Next State Output A(t) B(t) x(t) A(t+1) B(t+1) y(t) 0 0 0 0 0 1 23rows (2m+n) rows 0 1 0 0 1 1 1 0 0 1 0 1 m: no. of FF n: no. of inputs 1 1 0 1 1 1 • For the example: A(t+1) = A(t)x(t) + B(t)x(t) B(t+1) =A (t)x(t) y(t) =x (t)(B(t) + A(t)) 0 0 0 0 1 0 0 0 1 1 1 0 0 0 1 1 0 0 0 0 1 1 0 0

45. State diagram convention Mealy Machine: In/out State Example: x/y’ x=1/y=0 x 1 01 AB 01 01 y 1 Mealy type output depends on state and input Moore Machine: to next state in State out Moore type output depends only on state

46. State Diagram for the example x=0/y=0 x=0/y=1 x=1/y=0 A B 1 0 0 0 x=0/y=1 Present State Input Next State Output x=1/y=0 A(t) B(t) x(t) A(t+1) B(t+1) y(t) 0 0 0 0 0 0 x=1/y=0 x=0/y=1 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 1 0 0 0 0 1 x=1/y=0 1 0 1 1 0 0 1 1 0 0 0 1 1 1 1 1 0 0 • Graphical representation of the state table:

47. Equivalent State Example 0/0 1/0 S0 S1 0/1 1/0 0/1 S2 1/0 0/0 1/0 S0 S1 0/1 1/0 • Are there other equivalent states? • Examining the new diagram,states S1 and S2 are equivalent since • their outputs for input0 is 1 and input 1 is 0,and • their next state for input0 is both S0 and for input1 is both S2, • Replacing S1 and S2 by asingle state gives statediagram:

48. Exercise: Derive the state diagram of the following Circuit A D Z Q Q C R B D Q Q C R 5V C D Q Reset • Clock Q C R • • Logic Diagram: Moore or Mealy? What is the reset state?

49. 5-5 Sequential Circuit Design ? O U T IN DA Comb. Crct. DB Design procedure Idea, New product Specification • Word description • State Diagram • State Table • Select type of Flip-flop • Input equations to FF, output eq. • Verification State encoding

50. Specification • Component Forms of Specification • Written description • Mathematical description • Hardware description language • Tabular description • Equation description • Diagram describing operation (not just structure)