1 / 12

Switching Module

Switching Module. May 28 th , 2015. Agenda. Switching Module Overview Reference Design Diagram Decoder Lock Monitor Running the Design. Switching Module Overview. Used to perform the SDI video switching for Rx reliability testing

fifi
Télécharger la présentation

Switching Module

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Switching Module May 28th, 2015

  2. Agenda • Switching Module Overview • Reference Design Diagram • Decoder • Lock Monitor • Running the Design

  3. Switching Module Overview • Used to perform the SDI video switching for Rx reliability testing • Combination of decoder module (decoder.v) and lock monitor module (lock_monitor.v) • Decoder module controls the transmitted SDI video signal from internal pattern generator • 3 groups of control signals are used to control the SDI pattern being transmitted • Mode (2 bits) • Int 1 (4 bits) • Int 2 (4 bits) • In-System Source and Probe are being used (in reference design) to control these 10 bits control signal • Lock monitor module monitors the frame locked and trslocked output signals from the SDI II receiver when receiving SDI video signal

  4. Reference Design Diagram

  5. Decoder • Switching time is 3 seconds by default • Can be changed by changing the SWITCH_TIME parameter (decoder.v) • Signal change will trigger a pulse to the lock monitor module indicating a new source has transmitted. • Four different mode are available for the user to select the desired switching pattern [For example: X = 3(0011), Y = 6(1011)] *Please refer to table in next slide for detail information on decoder value “Int 1” and “int 2”

  6. Decoder Setting

  7. Lock Monitor • The trs locked and frame locked monitor time(1) is 500ms and 1 second, respectively by default • Monitor lock time can be changed by changing the TRS_LOCKTIME and FRAME_LOCKTIME parameter (lock_monitor.v) • The monitor time includes latency of SDI II Tx+ loopback cable + SDI II Rx • Number of errors will be counted via the signals trs_lock_error and frame_lock_errorif the trs or frame doesn’t get locked (signal trs_locked and frame_locked doesn’t get asserted) when SDI signal is received (1) There is no requirement for trs locked and frame locked time in SDI Standard of SMPTE

  8. Running the Design • Download and unzip the reference design file (s5gxsdi_ii_switching_module.zip) in your local project directory. • Launch the Quartus II software. • On the File menu, click Open Project. Select the s5gxsdi_ii.qpf project file from the project directory and click Open. • On the Processing menu, click Start Compilation.

  9. Running the Design • Set up the Board as below • Program s5gxsdi_ii.sof into the FPGA • Open Spf1.spf located in output_files folder to set the desired mode, int 1 and int 2 • Open stp1.stp to check the test result

  10. In-System Sources and Probes Decoder value set by user

  11. SignalTapTest Result Tx format being selected to Internal pattern generator Switching pattern set by user in In-system source and probe Monitoring the frame_locked and trs_locked Number of error (cannot be locked) found

More Related