GROUP MEMBERS Muhammad Talha Islam 2010-TE-054 Karim Akhter 2010-TE-123

1. GROUP MEMBERS Muhammad Umer Khalid 2010-TE-022 Muhammad Arif 2010-TE-010 GROUP MEMBERS Muhammad Talha Islam 2010-TE-054 KarimAkhter 2010-TE-123 Huffman Implementation on FPGA and Its Application in Image Compression Telecommunication Engineering Department ADVISOR: S.M. UMAR TALHA www.fpga-fyp.weebly.com PROJECT DIAGRAM • PROJECT OBJECTIVE: • The primary objective of this project is to implement Huffman algorithm on FPGA, and use this algorithm in multimedia compression like JPEG. • Reduce the amount of data required. • To minimize the redundancy • Use of an optimal entropy encoding lead the most redundant code OVERALL SYSTEM DIAGRAM PROJECT OBJECTIVE • PROJECT GOALS: • Implementation of Huffman algorithm on FPGA. • Reduce the amount of data required to represent image. • To minimize the redundancy. • Use of an optimal entropy encoding lead the most redundant code. PROJECT GOALS • METHODLOGY • Literature Review • The very first stage is more related to the literature review, the execution of this phase will begin by establishing the criterion that the system will need to meet its objectives. • Implementation Phase • In this phase, the proposed code will be implemented on software and the proposed Huffman algorithm is synthesized using Spartan 6 FPGA Kit. As a whole the encoder will be written in verilog, implemented and tested using Xilinx Spartan 6 development board • Testing Phase • The Huffman encoder will be tested using predetermined bit stream and specifically-aimed coded sequences. We will give the coded data from computer to our hardware. • In a digital communication we are concerned about Some key issues, that is the efficiency with which information from a given source can be represented another issue pertains to the rate at which information can be transmitted reliably over a noisy channel. These key aspects deal with mathematical modeling and analysis of a communication systems. Real time implementation of different encoder/decoder requires fast hardware architecture variety of design based on ASIC, DSP and FPGA. FPGA is one of the most widely used for real time hardware implementation. METHODOLOGY COMPONENTS • COMPONENTS • HARDWARE: • Xilinx Spartan®-6 LX45 FPGA in a 324-pin BGA package • Micro computer • SOFTWARES: • HDL editor • Verilog Programming ...Language • Matlab • ISE BACKGROUND CONCLUSION CONCLUSION: In this project we will do hardware implementation of Huffman encoder suitable for JPEG compression. The encoder will be written in Verilog, implemented and tested using Xilinx Spartan 6 development board. Eventually, it will be possible to merge these des Miceiigns to build encoder that is capable of generating decompressed files that may be compressed using standard implementation of JPEG compression standard. Eventually, it will be possible to merge this algorithm to build a encoder that is capable of compressing files that may be de compressed using a standard implementation of JPEG encoder. MODULE USED IN SYSTEM • MODULE USED IN SYSTEM: • The Spartan-6 LX45 is optimized for high-performance logic and offers: • 6,822 slices, each containing four 6- input LUTs and eight flip-flops ·Memory (LUTS) • 2.1Mbits of fast block RAM · four clock tiles (eight DCMs & four PLLs) • six phase-locked loops · 500MHz+ clock speeds • 58 DSP slices