1. Power Issues in Embedded Systems Wong Weng Fai

2. Outline • The Big Picture • Who’s got the Power? • What’s in the bag of tricks? Embedded Seminar

3. The Big Picture • Phenomenal increase in processor speed • 3GHz Pentium 4 by the end of the year • Shrinkage in size • Mobility highly desired • BUT battery technology not improving at the same rate Embedded Seminar

4. Batteries Not Included • Nickel-based batteries • Nickel-Iron • The first rechargeable, old technology • Nickel-cadmium and Nickel-Metal-Hydride • High energy density – good for motors • Lithium-based batteries • Promising because lithium releases electrons easily • Problem with battery life, dangerous to handle • Others • Zinc-air batteries – can work a laptop for 10 hours Embedded Seminar

5. Some Terminologies • Power is the rate of energy consumption • Power ≠ energy • Energy depends on how long you run the thing! • Optimizing for speed = optimizing for energy? • Some researchers look at average power Embedded Seminar

6. Back to Basics Gate oxide insulator Gate   N+ source  N+ drain        P- substrate  N-Channel Metallic Oxide Semiconductor Field Effect Transistor

7. Back to Basics – ACTION!       Gate oxide insulator - + Gate           +                 N+ source N+ drain   -           P- substrate  N-Channel Metallic Oxide Semiconductor Field Effect Transistor

8. CMOS VDD P-channel MOSFET Input: 0 = 0V 1 = +5V Output CMOS Inverter N-channel MOSFET GND Embedded Seminar

9. CMOS VDD P-channel MOSFET Input: 0 = 0V Output = 0 CMOS Inverter N-channel MOSFET GND Embedded Seminar

10. CMOS VDD P-channel MOSFET Input: 1 = +5V Output = 1 CMOS Inverter N-channel MOSFET GND Embedded Seminar

11. Power in CMOS P = total power VDD = supply voltage f= clock frequency N = switching (gate transition per clock cycle) Ileak = leakage power Istatic = static power QSC = quantity of charge carried by short-circuit current per transistion Embedded Seminar

12. Switching power Short-circuit power Leakage power Static power Static power Dynamic power Power in CMOS Embedded Seminar

13. Switching Power • Accounts for most (90%) of power • Two major factor is supply voltage and frequency • Voltage scaling • Frequency scaling Embedded Seminar

14. Short Circuit Power • During switching, there is a short period of time when both gates are ON  a path from VDD to ground  power dissipation Embedded Seminar

15. Leakage Power • Diode leakage • Source (and drain) together with substrate forms a diode • At times, this diode can be reverse-biased during which current can leak • Sub-threshold leakage • Even when gate is not completely on, enough of a channel can form for some movement of charges from source to drain Embedded Seminar

16. Static Power • Reduced voltage feeding • Both gates can be “weakly on” • Weak current flow from VDD to ground • Other parasitic current flows • Due to imperfect manufacturing or operating conditions Embedded Seminar

17. A Digression – The Problems Of Scaling down • Latch-up effect • Short-channel effect • Punch-through effect • Hot electron effect • Gate erosion Embedded Seminar

18. Latch-up Effect Embedded Seminar

19. Tricks in the bag • Voltage Scaling • Frequency Scaling • Power Gating Embedded Seminar

20. Voltage Scaling • Lower VDD • For the same circuit and technology, this leads to higher gate delay • Total delay, , is made up of two components,  = 1 + 2 • 1 is a constant • 2 VDD Embedded Seminar

21. Frequency Scaling • Widely used in many processors • Intel SpeedStep on mobile processors • Leads to lower performance • Obvious! Embedded Seminar

22. Power Gating • Turn off power to parts of the circuit • Can be problematic for circuits with memory Embedded Seminar

23. What About Memory? • SRAM • Implemented using CMOS • DRAM • Entirely different technology • Implemented using capacitors Embedded Seminar

24. SRAM CMOS SRAM Cell Embedded Seminar

25. DRAM Single Transistor DRAM cell

26. Model or Measure? • Hardware measurement • Measures the amount of current consumed • Depends on how the circuit is designed • Cannot get core CPU power breakdowns Embedded Seminar

27. Software Estimation • SPICE simulation • Very slow • PowerMill from Synopsys • CAD Tools • Part of a lot of CAD tool chains, eg. Synopsys • Architectural based simulation • Eg: SimplePower, WATTCH etc. Embedded Seminar

28. Putting it Together – System Power Reference: Marc A. Viredaz and Deborah A. Wallach, “Power Evaluation of a Handheld Computer: A Case Study”. Compaq Western Research Lab Technical Report 2001/1. May 2001. http://research.compaq.com/wrl/techreports/abstracts/2001.1.html Embedded Seminar

29. Dealing with it • System / OS • Algorithms • Architecture • Circuit/Logic • Technology Embedded Seminar

30. Technology • Low threshold, low voltage • Various technological issues as discussed Embedded Seminar

31. Circuit/Logic • Even within CMOS, there are different types of logic families that consumes different amount of energy • Transistor size • Layout • Asynchronous circuits • Clocking consumes a lot of power • Pipeline retiming Embedded Seminar

32. Architecture / Compiler • Trade off area for power Embedded Seminar

33. Architecture / Compiler • Trade off area for power • Shorter wires less power • Parallelism and concurrency • Directives to allow compiler to do • Voltage scaling • Frequency scaling • Power gating • One more degree of freedom: activity Embedded Seminar

34. Algorithms • Low power algorithms • Parallelism and concurrency • A under-research area Embedded Seminar

35. System / OS • System level power management • Heuristics for transiting between various power modes • Operating environment sensitive power management • Battery or plugged-in? • Power-domain specific management schemes Embedded Seminar

36. Reducing Processor Power • Energy conscious code generation • Reduce switching • Instruction scheduling • Use of Gray code instead of binary • Low power modes • Instruction compression • Parallelism and concurrency Embedded Seminar

37. Reducing Memory Power • Reduce memory accesses • All compiler techniques for reducing cache misses • Use registers • Memory reference compaction • Power aware page allocation • Group active pages together Embedded Seminar

38. Reducing Peripheral Power • Communication • Different power modes for communicating devices • Data compression • Adaptation in view of traffic and power • Disk • Spin-down and different power modes (when?) • Display Embedded Seminar

39. Summary • Some research opportunities still exist • Especially in algorithms and operating systems • An integrated approach is needed • All levels of the system cooperating with one another Embedded Seminar