1 / 9

Unit 11 Latches and Flip-Flops

Unit 11 Latches and Flip-Flops. Ku-Yaw Chang canseco@mail.dyu.edu.tw Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh University. Outline. 11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch 11.4 Edge-Triggered D Flip-Flop 11.5 S-R Flip-Flop

garvey
Télécharger la présentation

Unit 11 Latches and Flip-Flops

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Unit 11Latches and Flip-Flops Ku-Yaw Chang canseco@mail.dyu.edu.tw Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh University

  2. Outline 11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch 11.4 Edge-Triggered D Flip-Flop 11.5 S-R Flip-Flop 11.6 J-K Flip-Flop 11.7 T Flip-Flop 11.8 Flip-Flops with Additional Inputs 11.9 Summary Latches and Flip-flops

  3. Flip-Flops with Additional Inputs • Additional inputs to set the flip-flops to an initial state independent of the clock • Clear input ClrN • Q = 0 • Preset input PreN • Q = 1 • Active-low • a logic 0 is required toclear or set the flip-flop Latches and Flip-flops

  4. Flip-Flops with Additional Inputs Latches and Flip-flops

  5. Timing Diagram for D Flip-Flop with Asynchronous Clear and Preset Latches and Flip-flops

  6. D Flip-Flop with Clock Enable • Driven by a common clock • Hold existing data even though the data input may be changing Latches and Flip-flops

  7. Outline 11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch 11.4 Edge-Triggered D Flip-Flop 11.5 S-R Flip-Flop 11.6 J-K Flip-Flop 11.7 T Flip-Flop 11.8 Flip-Flops with Additional Inputs 11.9 Summary Latches and Flip-flops

  8. Q+ = S + R’Q (SR=0) Q+ = GD + G’Q Q+ = D Q+ = D · CE + Q · CE’ Q+ = JQ’ + K’Q Q+ = T  Q = TQ’ + T’Q (SR latch or flip-flop) (gated D latch) (D flip-flop) (D-CE flip-flop) (J-K flip-flop) (T flip-flop) Summary Latches and Flip-flops

  9. Homework #4 • 11.5 • 11.6 • 11.7 • 11.8 • 11.9 • 11.1 • 11.2 • 11.3 • 11.4 Paper Submission, due on May 13, 2004. Late submission will not be accepted. Latches and Flip-flops

More Related