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Overview of Transactional Memory: Principles and Challenges in Multicore Architectures

This document provides a comprehensive overview of transactional memory (TM) concepts, principles, and challenges, particularly relevant to multicore processor architectures. It discusses the need for performance enhancements in parallel software and identifies common issues related to locking mechanisms, such as deadlocks and priority inversion. It introduces TM's core properties, including atomicity and serializability, and explores how transactions work using private copies of shared data and conflict detection methods. It highlights TM's architectural requirements, implementation strategies, and current research directions.

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Overview of Transactional Memory: Principles and Challenges in Multicore Architectures

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  1. Transactional Memory Overview Olatunji Ruwase 15-740 Fall 2007 Oct 4 2007

  2. Future PCs are Multicore

  3. Parallel s/w for performance • Locks • Deadlocks • Priority Inversion • Buggy • Convoy Effect • Limited concurrency

  4. Transactions • Borrowed from Databases • Definition : A transaction is a finite sequence of machine instructions executed by a single process, that satisfies the following properties • Atomicity • Serializability Herlihy and Moss. “Transactional Memory: Architectural Support for Lock-free Data Structures, ISCA’93

  5. How transactions work • Make private copy of shared data • Make updates on private copy • If shared data is unchanged • Update shared data with private copy • Else conflict has occurred • Discard private copy and repeat transaction

  6. Requirements for supporting transactions • Buffering • Conflict detection • Abort/Rollback • Commit

  7. Transactional Memory • Herlihy and Moss, ISCA ’93 • ISA changes • LT,LTX, ST, COMMIT, VALIDATE, ABORT • Fully associative transactional cache • Per processor • Contents are exclusive of regular cache • Cache coherence protocol changes • Transactional cache line states • Transactional bus messages • Snoopy bus based implementation

  8. TM support for transactions

  9. Transactional Cache • Fully set associative cache • Each cache line can be in only one of transactional or regular cache • Holds transactional writes • Transactional writes are hidden from other processors and memory • Makes updated lines available for snooping on COMMIT • Invalidate updated line on ABORT

  10. CPU Herlihy and Moss, ISCA ‘93 Memory Cache Transaction Cache

  11. Sample Counter code

  12. Exposing more concurrency • Doubly linked list implementation of queue • Head, Tail pointers • If queue not empty • Only head pointer is used for dequeuing • Only tail pointer is used for enqueuing • Concurrent enqueuing/dequeuing • Possible in TM • Not possible with locks

  13. Challenges of TM • Long transactions • I/O • Nested transactions • Interrupts

  14. Other TM Ideas • Speculative Lock Elision • Software Transactional Memory • Requires no hardware changes • Allows composition of transactions

  15. Speculative Lock ElisionRavi and Goodman, MICRO ‘01 • Speculatively remove lock acquire and removal instructions • Microarchitectural changes • No changes to cache systems • No changes to ISA • Can work with existing lock based code

  16. SLE example

  17. Credits for slides • Bryant Lee (CMU) • Transactional Memory: Principles and Current Research • Colin Blundell (UPenn) • Transaction Memory Overview • Kevin Moore (UW) • Thread-Level Transactional Memory

  18. Compare TM and TLS • TM is optimistic synchronization • TLS is optimistic parallelization • Any other similarities or differences

  19. Questions/Discussions

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