Advanced Embedded Systems

1. Advanced Embedded Systems Lecture6 Embedded Systems CPU

2. Advanced Embedded Systems The SAB 8xC166 microcontrollers • The SAB 8xC166 family is made of 2 circuits: • 80C166: microcontroller without internal program memory; • 83C166: microcontroller with internal program memory; • The main features are: • Most of the instructions necessitates 1 cycle (100 ns) for their execution; • Hardware support for context switching in a single cycle; • Von Neumann architecture with 256 Kbytes addressing space; • Possibility of detecting stack over and underflow; • 3 flexible bus configurations; • 2 types of interrupts: classical and very fast (PEC); • Internal periphery: A/ D converter, 5 general purpose timers, 16 capture/ compare channels, 2 USART interfaces, programmable watchdog; • 76 individual input/ output lines; • Development support: C compiler, assembler, link-editor, simulator, in-system emulator, development kit;

3. Advanced Embedded Systems

4. Advanced Embedded Systems • The figure presents the central unit of the microcontroller: • The instructions are executed in a 4 stages pipeline, hence most instructions are executed in a single cycle (100 ns at a clock frequency of 25 MHz); • The Barrel Shifter module ensures that any rotation, with any number of ranks, be executed in one single cycle; • The central unit contains also an UAL and a stack situated in the internal memory;

5. Advanced Embedded Systems • The stack pointer, SP, ensures the access at the stack; • 2 other registers, STKOV (“Stack Overflow”) and STKUN (“Stack Underflow”) delimitates the stack and are used for detecting the over and the underflow of the stack, respectively; • The context of the machine is kept in a group of 16 context registers, GPR (“General Purpose Registers”), mapped in the RAM memory space; • There are several groups of context registers, this being a useful feature for fast switching the context, for example in the case of interrupts; • The active group is indicated by the register CP (“Context Pointer”) which indicates the base address of the active GPR group; switching the context can be done simply by changing the content of the CP register; • The number of the register groups is limited only by the dimension of the RAM memory; • The groups can be overlapped this being a useful feature in case of transferring parameters; • There are busses for accessing the 2 types of internal memories;

6. Advanced Embedded Systems • Memory organization • It is Von Neumann type, that is there is a single memory space including the internal memories, the special function registers and the external memory; • The total space has 256 Kbytes and is divided in 4 x 64 Kbytes segments; each segment is divided in 4 x 16 Kbytes pages; • The fig. shows the memory organization:

7. Advanced Embedded Systems • There are several predetermined zones; e.g., 00000 – 000BFH, from code segment 0, contains the interrupt vector table; • The internal ROM memory exists only in the 83C166 circuit; • By reading two external terminals, at the initialization, the CPU finds out if the internal ROM is activated or not; • The internal RAM memory has 1 Kbytes and contains the stack, the GPRs and the source and destination pointers for the PEC transfers; allows bit access in certain parts of it; • The stack is accessed through SP, the stack pointer, and has variable dimension (32, 64, 128 or 156 bytes), through a field from the control register; • The external memory can be used for code or data and is organized as 4 64 Kbytes segments; by reading the same 2 terminals, at the initialization, the CPU finds out if the external memory is activated or not;

8. Advanced Embedded Systems • There are 2 registers, STKOV and STKUN, which delimitates the upper and lower bounds; an internal interrupt is generated if the bounds are outrun; • The GPR group can be situated anywhere in the internal RAM; several GPR groups exist, their number being limited only by the capacity of the internal RAM; only one GPR group is active, at a given time moment, and the CP register indicates the active GPR group; • The GPR group is made by 16 bit 16 registers, R0 – R15, the first 8 being accessible also at byte level; they allow bit access too; the GPR group contains the state of the machine and changing the GPR leads to a context switch; • An area of 512 bytes is reserved, in the RAM memory, for the general purpose registers; bit, byte and word accesses are allowed; • Part of these registers controls the CPU; thus, the SYSCON register (“System Configuration”) is used for fixing the features of the external cycle (duration, signals duration, activation or not of the READY signal), the external cycle type, the stack dimension, the validation or not of the external memory;

9. Advanced Embedded Systems • The PSW (“Processor Status Word”) register contains the condition registers, a bit which enables or not the whole interrupt system, a bit at the user disposal and 4 bits for coding the priority level of the current interrupt request; • The IP register (“Instruction Pointer”) shows the address of the next instruction, in the current code segment; this is indicated by the CSP register (“Code Segment Pointer”), more exactly by two of its bits, which will be the most significant two bits of the address (A18 and A17); • The memory is divided in segments and each segment is divided in 4 x 16 kbytes pages; • Other SFR registers are: CP, SP, STKOV, STKUN … • The internal periphery • Is made by: a capture/ compare unit, GPT general timers, the A/ D converter, the serial interfaces and the watchdog counter; • The periphery is controlled by the CPU and is interfaced to the exterior through the SFRs; • The CPU and the periphery have different clocks;

10. Advanced Embedded Systems • The capture/ compare unit

11. Advanced Embedded Systems • Is useful for operations such as: digital signals generation, generation of signal with variable length, measurement of the moments when certain events occur, measurement of signal durations and so on; • It consists in 2 x 16 bit counters, T0 and T1, each with its own loading register and connected to a group of 16 capture/ compare registers; • The clock for the 2 counters is obtained from the system clock divided by a programmable counter, from an output of the T6 counter from the GPT2 group or from an external source; • Each capture/ compare register can be individually programmed and can be allocated either to counter T0 or to counter T1; • A dedicated terminal from port P2 corresponds to each register; it is input if the capture operation was requested; when the signal occurs the content of the correspondent counter is loaded in the register corresponding to the terminal; • When the compare operation was requested, the content of a register is compared with T0 or T1, and when they are equal a transition occurs at the terminal of the P2 port which corresponds to the register;

12. Advanced Embedded Systems • The T0 and T1 counters have the role of time base, with a resolution of 400 ns, for the capture/ compare registers but can work also as independent counters; • They are controlled by a SFR, T01CON; this enables their functioning, chouses the operating mode and chouses the clock; • Each register counts up from a programmed value which is reloaded at the end of the cycle; • When a counter overflows, an indicator is activated for each counter; it can request an interrupt or a PEC, if this one is enabled; each counter has an own interrupt control register and interrupt vector; • There are 4 capture and 4 compare variants; • By program one may request to each register positive front capture, negative front capture or both positive and negative fronts capture; thus, a large number of applications are covered; • At compare, different features exist: one may program, for each register, to react if the equality is met several times in a cycle, only once in a cycle, without modifying the associated terminal or with modification in several manners;

13. Advanced Embedded Systems • The general purpose counters, GPT • It is a flexible group of counter/ timers, useful for a large number of applications, such as: event counting, measurement of signals duration, signals generation, frequency multiplication or division etc. • GPT is divided in 2 groups: GPT1 and GPT2; • GPT1 is made by 3 x 16 bit counters, T2, T3 and T4; each one can be programmed to operate as a counter, a timer or a commanded counter; • The timer mode is useful for temporizations, the counter mode is useful for counting external events and the commanded counter mode is useful for counting events in a window delimitated by external signals; • The T2 and T4 counters can be configured as capture registers and reload registers for the T3 counter; • GPT2 is made by 2 x 16 bit counters, with the same operating modes and a separate capture/ reload register; • The counters for both groups can work independently or can be concatenated; • The counters can be sources for interrupts, with separate vectors and control registers; • Ports are associated to the counters;

14. Advanced Embedded Systems

15. Advanced Embedded Systems • The A/D converter • The A/D converter has 10 channels, 4 operating modes and the duration of a conversion is 9.7 μs; • The analog inputs are the terminals of port P5; • The converter is controlled by the ADCON (“Analog/ Digital Control Register”) register; it selects the input, chouses the operating mode, starts and stops the conversion and shows the state of the converter;

16. Advanced Embedded Systems • The conversion’s result is obtained in the ADDAT (“Analog/ Digital Data Result Register”) register; the 0 – 9 bits are the result and the 12 – 15 bits indicates the active input; data must be read out from the CPU until the next conversion; • The converter can operate in one of 4 modes: • Single Channel Conversion: after programming, a conversion takes place on the selected channel, at its end an interrupt is requested and the channel stops; • Single Channel Continuous Conversion: the conversion is repeated until the converter is stopped by program; the interrupt request is generated after each conversion; • Auto Scan Conversion: a sequence of entries can be established; at the end of the sequence, the interrupt request is generated and the converter stops; • Auto Scan Continuous Conversion: the sequence is repeated until the program stops the converter; the interrupt request is generated after each conversion; • The converter can generate an interrupt request, if enabled; it owns a control register and an interrupt vector;

17. Advanced Embedded Systems • The serial interfaces: • 2 serial interfaces: ASC0 and ASC1; they can operate in: • Asynchronous mode: full duplex at 625 kbps rate; • Synchronous mode: half duplex at 2.5 mbps rate; • In asynchronous mode: • Formats with 7,8 or 9 data bits can be used, with or without parity control and 1 or 2 stop bits; • Parity, rhythm and frame errors are detected and an interrupt indicator is activated; • The design of multimicrocontroller systems is facilitated, due to the 9th bit; • Support for testing through the loopback mode is offered; • Each interface has its own interrupt vectors for reception, transmission and errors; • The serial interfaces are controlled by control registers S0CON and S1CON (“Serial Control Register” 0 and 1); they select the operating mode, enables the reception and the parity, rhythm and frame controls and installs the loopback mode; • The writing is done through data buffers S0TBUF and S1TBUF;

18. Advanced Embedded Systems • The reception is done through a double buffer; high speed is obtained by superposing the storing of the character from the serial line with the transfer of the previous character to the CPU; • Both interfaces can operate in asynchronous mode; the terminals used are RxD0/P3.11, TxD0/P3.10, RxD1/P3.9 and TxD1/P3.8; there are several formats: • 8 data bits, without parity; • 8 data bits + parity bit; • 7 data bits + parity bit; • 9 data bits, without parity; • 8 data bits + wake-up bit: characters with 9 bits are transferred; at reception the character is loaded in the reception buffer only if the 9ty bit is logical 1; otherwise the character is discarded and the interrupt indicator is not activated; this feature is the base for master – slave multimicrocontroller systems; • Both interfaces can operate in synchronous mode; the terminals TxD0/P3.10 and TxD1/P3.8 are used for generating the clock and the other two terminals are used for transferring data; • The transferring rate is programmable;

19. Advanced Embedded Systems • The watchdog counter • It was foresight for deblocking the processor from a not operational situation in which the processor entered due to a software error or a hardware fail; • If the program does not load the watchdog in a predetermined amount of time, it will generate an internal and external reset initializing the processor and, possibly, also the rest of the system; the time domain is 25.6 μs – 419 ms in several steps; • The watchdog counter is made by a 16 bit counter which receives a clock obtained from the system clock divided by 4 or 256;

20. Advanced Embedded Systems • The external cycles • Several types of external cycles can be executed; they differ by several programmable parameters, thus allowing the connection of many memory circuits and avoiding, as much as possible, the waiting states; • By reading two external terminals, EBC 0,1 (“External Bus Configuration 0, 1), during the RESET signal, the CPU can install 1 of 4 cycles: • Single Chip mode; • 16/ 18 bit Address, 8 bit Data, Multiplexed Bus; • 16/ 18 bit Address, 16 bit Data, Multiplexed Bus; • 16/ 18 bit Address, 16 bit data, Non – Multiplexed Bus; • Single Chip mode: the accesses are done only internally, as a consequence the P0, P1 and P4 ports can be used as general purpose I/ O ports;

21. Advanced Embedded Systems • 16/ 18 bit Address, 8 bit data, Multiplexed Bus:

22. Advanced Embedded Systems • 16/ 18 Address, 16 bit Data, Multiplexed Bus: the memory is implemented in one module;

23. Advanced Embedded Systems • 16/ 18 Address, 16 bit Data, Multiplexed Bus: the memory is implemented in two modules;

24. Advanced Embedded Systems • 16/ 18 Address, 16 bit Data, Non-Multiplexed Bus: the memory is implemented in one module;

25. Advanced Embedded Systems • 16/ 18 Address, 16 bit Data, Non-Multiplexed Bus: the memory is implemented in two modules;

26. Advanced Embedded Systems • The ports: • There are 6 I/ O ports with 76 lines; • The ports 0 – 3 have 16 bits, the port 4 has 2 bits and the port 5 has 10 bits; the bits of ports 0 – 4 can be set as inputs or outputs, independently; • All the ports have also alternative functions: • The ports 0 and 1 are used as addresses and data, in case of external memory cycles; the port 4 contain the most significant two bits of the address when the segmentation is enabled; • The terminals for port 2 are used as inputs, in capture mode, or outputs, in compare mode; • The terminals of port 3 are used for commanding the counters T0 and those from group GPT, for serial transfers, for the signals /WR, /BHE and /READY; • The terminals of port 5 are used as analog inputs; • Each of the ports 0 – 4 have its own data register, P0 – P4, and its own data direction register, DP0 – DP4, for setting each line as input, output or high-impedance input; • Port 5 is only input, therefore it has not data direction register;

27. Advanced Embedded Systems • Microcontroller initialization • Externally: through input /RSTIN; • Internally: through instruction SRST or through the watchdog module; a signal occurs on the terminal /RSTOUT; it can be used for initializing the rest of the system; • Low power modes • Idle: it’s a soft low power mode; the CPU is stopped but the rest (memory, periphery) remains active; the mode is entered through a privileged instruction and is leaved through an external Reset or an external interrupt; • Power down: it’s a hard low power mode; the whole circuit is stopped, the content of the internal RAM memory is maintained; the mode is entered through a privileged instruction and is leaved through an external Reset; two measures were foresight for avoiding the accidentally entrance in this mode: • The instruction is privileged; • The instruction is active only if the /NMI input is active; this offers a synchronization mechanism between the entrance in the Power Down mode and an external event such as a following power down;

28. Advanced Embedded Systems • External bus timing control: timing characteristics can be programmed for covering a wider group of memory circuits and for avoiding external wait circuits; • Memory Cycle Time: Wait states can be introduced for slowing down the processor; additional delay of 0 – 750 ns (at fOSC = 40 MHz) can be introduced; the memory cycle time can be varied as follows: • 150 – 900 ns, at fOSC = 40 MHz, in case of multiplexed bus modes; • 100 – 850 ns, at fOSC = 40 MHz, in case of non-multiplexed bus modes:

29. Advanced Embedded Systems • Memory Tri-State Time: • Is the time required by the memory to release the bus once the memory read (/RD) signal has been disserted; it determines how quickly one memory access can follow another one; • 1 or 2 Memory Tri-State Time Wait states can be introduced (50 – 100 ns, at fOSC = 40 MHz);

30. Advanced Embedded Systems • Read/Write Signal Delay • Represents the period of time between the falling edge of the Address Latch Enable (ALE) signal and the falling edge of the read (/RD) or write (/WR) signals; • If no additional Read/Write Delay is programmed the falling edges of the signals ALE, /RD or /WR coincide; • A quarter of a machine cycle (25 ns at fOSC = 40 MHz) can be introduced as a delay offering more time to memories and peripherals; • All the mentioned parameters can be programmed through fields from the SYSCON register: MCTC, MTTC, RWDC; • External Data Ready Signal: • If the Data Ready function is enabled, the duration of the external accesses is not determined by the contents of the MCTC field in the SYSCON register, but by the state of the /READY input pin; • In this case the /READY input pin must be correctly activated for every external memory access; • Activated through the RDYEN bit from SYSCON;

31. Advanced Embedded Systems

32. Advanced Embedded Systems • Programming • Addressing modes: • Immediate addressing: 1 or 2 operand bytes follow the code byte or bytes; • Direct addressing: the address of the operand follow the code bytes; the address is on 4, 8, 12 or 16 bits; • Extended addressing: similar with the previous one but the address is now 18 bits long; • Indirect addressing: after the code bytes a byte specifying a register from the active GPR group; this register contains the 16 bit address of the operand; • Register addressing: when the operand is in one of the GPR registers; requires only 4 bits; • Relative addressing: is used by some jump instructions; the destination address is obtained adding an 8 bit offset to the content of instruction IP • Based addressing: most instructions use it: for accessing a register from GPR with CP, for accessing a SFR, for accessing the last 128 RAM bytes;

33. Advanced Embedded Systems • Instruction set • Arithmetic instructions • Logical instructions • Boolean Bit Manipulation instructions • Compare and Loop instructions • Shift and Rotate instructions • Prioritize instructions • Data Movement instructions • System Stack instructions • Jump and Call instructions • Return instructions • System Control instructions: resetting the microcontroller, entering the Idle mode, the Power Down mode, servicing the Watchdog Timer, disabling the Watchdog Timer, signifying the end of the initialization routine; • Miscellaneous

34. Advanced Embedded Systems • Support tools: hardware support and software support; • Hardware support: • In-Circuit Emulator (ICE): emulates, in real-time, the execution of an application program and provides the hardware stimuli characteristics to the microcontroller; functions: • Real-Time: the emulator executes the application program in the target system, with the target systems original clock, without wait states; • Memory: 256 Kbytes; • Host Link: fast downloading and uploading from/to the host are ensured; • Trigger Conditions: facilities for tracing and for breakpoint triggers are offered; trigger conditions are: IP addresses, IP ranges, opcode values, operation results and operand addresses; • Tracing: a trace buffer for capturing trace information in real-time exists; trace on and trace off capability exists to allow only selected portions of code executed during emulation; • Single Step: single instruction or HLL statement execution; • Counter Value: a counter can be used in conjunction with triggering conditions to count events; • Symbolic debugging: alphanumeric symbols instead of absolute addresses;

35. Advanced Embedded Systems • Software support: • Assembler package: a macro-assembler, a linker, a locator, a library manager and an object-to-hex converter; • The macro-assembler have features such as: generating relocable code, supporting macros with optional parameters, supporting conditional assembly, supporting program modules and data classes, generating optional lists, generating object file with information for use by other tools; • C Compiler: implements the standard C language with additional support for specific internal features of the SAB 8xC166; • It allows for different configurations of memory usage including single chip configuration; • The output is assembler code with symbols, line numbers and module names included for symbolic and high level language debugging; • Optional optimizers can be enabled to provide either code density or execution speed optimization; • Simulator package: allows to debug software and to determine the amount of time required for a piece of code to be executed; provides the ability to control and monitor the execution of the software through the use of triggering conditions.