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U of U NAND Design Project

U of U NAND Design Project. Senior Project Proposal Presentation. NAND Project. The Problem… Emerging and future applications will require NAND to continue to function well beyond 100K program/erase cycles, the point at which there is no manufacturer guarantee of error free functionality

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U of U NAND Design Project

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  1. U of U NAND Design Project Senior Project Proposal Presentation

  2. NAND Project • The Problem… • Emerging and future applications will require NAND to continue to function well beyond 100K program/erase cycles, the point at which there is no manufacturer guarantee of error free functionality • SLC specifications for endurance life are standardized (typically 100K cycles), but very little industry wide characterization exists to show how long SLC NAND can continue to function (300K, 500K, 1M+ cycles, etc.) • Each unique NAND design, vendor, and fab process will demonstrate different failure mechanisms and behavior • World needs a low cost, simple, platform that can experimentally find the failure behavior of NAND as it gets high usage, i.e.“worn” • Understand bad bit/block behavior as a function of wear, +type of failure (read disturb, program disturb, program/erase cycle wear out, etc.)

  3. What Does this do for Industry? • Enables product designers to build better products with NAND • Accelerate failure analysis in applications with NAND • Understand cycle limitations of a particular design and in turn build better products that last longer • Plan for graceful device degradation in product designs • Understand bad blocks incurrence over life of product • Determine amount of ECC to achieve required lifespan • Consider the effects of wear leveling on a part

  4. NAND Project Objectives • Build a simple, flexible, bench top platform for SLC NAND endurance cycle-life testing • Create separate modular functions that can: • Erase • Check for erase failure flag (via Read Status Command) • Verify an erase status failure by reading the failing block and checking for all 0’s • Program Page • Verify programming was successful (via Read Status Command) • Read Page (discard what is read- for read disturb cycling) • Read Verify - compare/verify a block against originally programmed pattern • The user should be able to input (via script, GUI, etc) the set of commands necessary to configure the test environment to perform any sequence of the above functions • User to specify the range of blocks of the device which are to be tested • User to specify the number of cycles that each function is to be repeated • User to select auto-generated random seed data, or be allowed to input a single pattern for device testing • Collect stats on failures and cycle counts

  5. Concept Diagram Host PC Basic GUI Config and control / setup Statistics Gathering Plot Utility / File Export Simple GUI USB ver 2.0 Seed Generation Prog/Erase/Read Function Modules USB Bulk Interface Basic Flash Controller Module FPGA Dev System Standard SLC NAND Daughter Board DUT

  6. Deliverables • H/W and GUI Documentation • BOM List • Daughter Board PCB Layout • Enough to Enable Someone to Recreate Entire Setup from scratch • Users Guide / Getting Started Guide • Example Configuration Setup / Scripts • Example output (up to 500K cycle data on std NAND)

  7. Stretch Goals • GUI • Plot Capability • UNIX capability • Compatibility for multiple NAND Manufacturers • Controller • Utilize cache commands • Utilize dual plane commands • Compatibility for multiple NAND Manufacturers • Daughter Board • Compatibility for multiple NAND Manufacturers

  8. RISKS • Controller Design • Timing Constraints / Data Corruption • System Integration • USB Interface • Testing Time • GUI Interface

  9. Group Communication Plan • Group Website http://www.eng.utah.edu/~jhamblin/4900/index4900.html • Weekly logs • Collaborative documents • Email • Weekly Meetings (Minimum)

  10. References • Micron Personnel (Dennis Zatteirro, Dean Klein, Ken Koenig) • Senior Project Design Recommendation for NAND Flash Integration in the PC (S. Brimley et. al.) • Micron Technology, Inc (2006)http://download.micron.com • Altera (n.d.) www.altera.com/education • Hennessy, J., Patterson, D. (2003) Computer Architecture: A Quantitative Approach, 3rd edition

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