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Challenges in High-Speed Link Chip Design: Bandwidth Limits and Channel Effects

Explore the complexities of designing high-speed link chips, including bandwidth limitations, line attenuation, reflections, and inter-symbol interference. Learn about the impact of various factors on signal quality and the challenges they pose.

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Challenges in High-Speed Link Chip Design: Bandwidth Limits and Channel Effects

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  1. ECE 679 -- Lecture #2 First slides: Prof. Stojanovic, MIT Last slides: Prof. Dally, Stanford

  2. What makes it challenging • Now, the bandwidth limit is in wires High speed link chip > 2 GHz signals

  3. Backplane environment • Line attenuation • Reflections from stubs (vias)

  4. Backplane channel • Loss is variable • Same backplane • Different lengths • Different stubs • Top vs. Bot • Attenuation is large • >30dB @ 3GHz • But is that bad? • Required signal amplitude set by noise

  5. Inter-symbol interference (ISI) • Channel is low pass • Our nice short pulse gets spread out • Dispersion – short latency(skin-effect, dielectric loss) • Reflections – long latency(impedance mismatches – connectors, via stubs, device parasitics, package)

  6. Error! ISI • Middle sample is corrupted by 0.2 trailing ISI (from the previous symbol), and 0.1 leading ISI (from the next symbol) resulting in 0.3 total ISI • As a result middle symbol is detected in error

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