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Write Clock (MCk) 40 Mhz

WRITE. Write Clock (MCk) 40 Mhz. Trig_x - (low: sampling window controls writing to sampling cells). width ~ 15 ns, trig to low just before clock rising edge. A/D CONVERSION. Clear_ADC (pulse clears register). width ~ 20 ns (sometime before ADC). Rp (pulse clears Cext).

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Write Clock (MCk) 40 Mhz

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  1. WRITE Write Clock (MCk) 40 Mhz Trig_x - (low: sampling window controls writing to sampling cells) width ~ 15 ns, trig to low just before clock rising edge A/D CONVERSION Clear_ADC (pulse clears register) width ~ 20 ns (sometime before ADC) Rp (pulse clears Cext) width ~ 20 ns (falling edge coinciding with ADC start) Ctrl_rd_x width ~ 2 us (time for ADC conversion) READ delta t (~ 5ns) Read Clock (Ck_rd) 40 Mhz . . . . width ~ 10 ns, sometime before passing token Clear_token width ~ 6.5 us (time to read out 256 cells) AD_x Tok_in must trigger on a read clock leading edge, width= 2*delta t

  2. READ Read Clock (Ck_rd) 40 Mhz

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