“ abcnasic ” SEU strategies

1. Simple ideas and proposals • Assumptions based on : • Tentative to limit the triplications where strictly needed • In criticality order “abcnasic” SEU strategies

2. Protection about the “DCL”functions An soft error on DCL may result in one or a few packets loss, if properly protected. One option would be the use of a watchdog synchronized to DCL_BUSY This has to be evaluated by model and simulation (Applying full triplication on the DCL logic would be a killer, because of the peak current activity) Watchdog “abcnasic” SEU strategies Write Busy Reset Read Readout Port FIFO L1Buffer DCL Read

3. Chip to chip data path chain on module/hybrid “abcnasic” SEU strategies ABCN-Last-2 data pending ABCN-Last-1 data pending To HCC T.fifo T.fifo WE WE ABCN-Last-1 ABCN-Last Header Data Header Data Header Data

4. Minimum service of the Readout function Actually the “Readout” is the most “”unknown” part for concerns about soft errors, but the function is critical (serializer has to be able to send packets) An option is to provide a “minimal” mode (after soft error or by addressable command) which is : BYPASS (to adjacent chip data : ie only passing data through w/o local chip interruption) This BYPASS mode should be fully soft error protected ADJ aCSR “abcnasic” SEU strategies Bypass (soft error or command) R3 Serializer Readout L1 bCSR

5. S. Bonacini CERN Dice Cell

6. S. Bonacini CERN Double DFF with interleaved subblocks to separate redundant nodes 4.5um Dice Cell The DICE cell is currently ported to the current version of the IBM 130nm cell library (not Artisan) by Filipe De Sousa