Understanding HAsim

1. Understanding HAsim • Michael Adler

2. Asim vs. HAsim Similarities • Configured with AWB • Split functional / timing • Timing driven • Minimum timing state: IP • Functional interface methods • Differences • Inherently spatial and parallel: • Timing model is modules (state machines) connected by serial channels • Distributed computation of time • Communication is expensive • Can’t pass a big ASIM_INST through all FIFOs • Pass token instead • No smart pointers • More careful management of token lifetimes

3. Asim vs. HAsim Model Structure Asim • Hierarchical modules • Central scheduler manages • Clock tree • Model parallelism • Named ports manage latency • HAsim • Flat module space • Distributed control • Time tracked locally (A-Port protocol) • Inherently parallel • Multiplexing controlled locally • Named ports manage latency and time

4. HAsim Dataflow: Latency Insensitive (LI) Channels • Each module is an independent state machine • All arrows are LI channels: • Functional channels are simple LI channels (FIFOs) • Timing channels are A-Ports (FIFO with latency and model time) Fetch Decode Execute Functional Fetch Functional Decode Functional Execute

5. Latency-Insensitive (LI) Channels • Lowest level LEAP channel • Named channel: • Endpoints are declared and LEAP makes the connection • Endpoints need not be on the same FPGA • Simple semantics: • FIFO • Unspecified buffering (at least one slot) • Unspecified latency, though on chip it is typically one cycle • Convenience functions build request/response pairs • Connection_Send#(CONTROL_MODEL_COMMIT_MSG) linkModelCommit<-mkConnection_Send("model_commits");

6. Timing A-Port • LI channel with timing model semantics • Receiver specifies latency • Internal buffering is at least latency * number of multiplexed instances • Model cycle is defined to be the number of messages passed through an A-Port • All readers/writers of A-Ports must honor this requirement • A-Port type is typically a Maybe#(<real type>) • tagged Invalid means no message but cycle advances • tagged Valid <data> is activity and cycle advances • PORT_RECV_MULTIPLEXED#(MAX_NUM_CPUS,DCACHE_LOAD_OUTPUT_DELAYED) rspFromDCacheDelayed<-mkPortRecv_Multiplexed("DCache_to_CPU_load_delayed", 1); rule stagex;let m_complete <- rspFromDCacheDelayed.receive(cpu_iid); if (m_complete matches tagged Valid .rsp) begin … endend

7. HAsim’s A-Port Library • Convenience wrappers for common idioms • Compositions of simple A-Ports A-Port Stage A Stage B Credit Stall Port • We will see another standard composition, permutation ports, later in on-chip networks

8. Distributed Control • Each module allocates a local controller • Takes start/stop/pause commands from software global controller • Determines which CPU instance is running in multiplexed modules • Arguments to mkLocalController are vectors of managed A-Ports • startModelCycle may fire when all inports have a message and all outports have space • module IFETCH; LOCAL_CONTROLLER#(MAX_NUM_CPUS) localCtrl <- mkLocalController(inports,outports); • rule stage0; • let cpu_iid <- localCtrl.startModelCycle(); …endrule • rule stageN;localCtrl.endModelCycle(cpu_iid, 1); …endruleendmodule

9. Multiplexed Models • Each HAsim pipeline may model many multiplexed instances • Implementation is similar to SMT: • Single instance of pipeline logic • Replicated state • Local controller returns the active instance IDlet cpu_iid <- localCtrl.startModelCycle(); …localCtrl.endModelCycle(cpu_iid, 1); • Multiplexing is currently round-robin • FIFOs are very efficient on FPGAs • Random access requires addressable storage – big area penalty

10. HAsim Packages • Standard Asim: AWB and simcore • LEAP: • Required: leap, leap-platforms • Optional: leap-debug, leap-examples • HAsim: • Required: hasim, hasim-models • Optional: hasim-alpha, m5, hasim-mips