Ultra DMA 66ATA/66 Eric Kvamme Manager, Desktop Interface Engineering firstname.lastname@example.org
Ultra DMA 66 Presentation Topics • Introduction to Ultra DMA • Ultra DMA Goals • Ultra DMA Protocol • Protocol Changes for Ultra DMA 66 • Ultra DMA Timing • Timing table • Required IC timings for Ultra DMA 66 • Timing precautions • System configuration recommendations for best margin • 80 Conductor Cable • Cable Detection Methods • BIOS and Driver Overview
Goals of Ultra DMA • Higher transfer rate • Increasing interface transfer rate keeps the interface from becoming a bottleneck for system performance as disk read channel rates increase. • Retain or improve reliability • False transitions on edges of control signals (e.g. DIOR-/DIOW-) can prevent systems from working at any speed. • Achieved through series termination and CRC checking. • Low cost implementation • Achieved by minimizing changes required to support protocol and through backward compatibility. • Continue to allow simple end-user configuration. • No hardware changes for Ultra 33 • New cable required for modes higher than 2 is only system configuration change seen by user.
Ultra DMA Protocol • The sender strobes the data to the recipient. • Unlike PIO and Multiword DMA where the host strobes data it receives (read data). • Synchronous sending of DATA and STROBE eliminates cable propagation delay and host/device interlock time as factor in setup and hold times. • Performs a check of data transfer integrity through CRC. • New "logical" control signals are created by redefining existing signals during an Ultra DMA burst. • Old New (read) New (write) • IORDY DSTROBE DDMARDY • DIOR- HDMARDY HSTROBE • DIOW- STOP STOP
Ultra DMA Protocol • Ultra DMA protocol is only active during a burst. • An Ultra DMA burst is defined from the assertion of DMACK- to the negation of DMACK- • Prior to assertion of DMACK-, signals have standard ATA functions. • After assertion of DMACK-, Ultra DMA signal definitions apply and normally illegal states (assertion of DIOR- and DIOW- simultaneously) occur. • Signals are returned to an idle state under their ATA functions before the negation of DMACK-. • Allows Ultra DMA devices to function with non-Ultra DMA aware devices.
Ultra DMA Protocol • Sender does not receive acknowledgment of each word sent to the recipient. • Both edges of the STROBE signal are used. • Transfer rate was doubled from Multiword DMA mode 2 to Ultra DMA mode 2 without increasing the frequency on the cable. • Any agent (device or host) that supports a particular Ultra DMA mode shall be able to receive data at the minimum tCYC for that mode. • The host no longer strobes words it receives so it shall be capable of accepting data at the minimum cycle time of the Ultra DMA mode it sets the device to. • Sender may send STROBE cycles as slowly as it desires without violating the protocol (no maximum tCYC time).
Ultra DMA Protocol • IDENTIFY DEVICE command informs host of: • Ultra DMA modes supported • The currently active Ultra DMA mode • Level sensed on PDIAG-:CBLID- during the device based cable detection if the device supports modes higher than 2. • Host uses SET FEATURES to activate/deactivate Ultra DMA. • Default DMA protocol shall be Multiword DMA, not be Ultra DMA. • SET FEATURES shall executed after power on and hard resets in order to program device to any Ultra DMA mode. • Executing a SET FEATURES for any Multiword DMA mode will deactivate Ultra DMA.
Ultra DMA Protocol • Initiating the Ultra DMA burst • A burst can only be initiated by the device. It does this by asserting DMARQ. • The host asserts DMACK- and negates STOP in response to the device’s assertion of DMARQ. • The burst transfer will begin with either the host (read command) or the device (write command) asserting DMARDY-. • Pausing the DMA burst • The DMARDY- signal is negated by the recipient to request a pause of the burst. • Because the sender needs to synchronize the incoming negation of DMARDY- before it stops sending STROBES, it may send additional words. • Because of system delays, the recipient may see up to 3 words after negating DMARDY- in the highest modes. • The sender shall pause if DMARDY- is negated by ceasing to toggle the STROBE signal. The sender may pause at any time by ceasing to toggle the STROBE signal.
Ultra DMA Protocol • Terminating the Ultra DMA burst • Either the host or the device can stop an Ultra DMA burst. Multiple control signals are involved in a termination and the sequence is dependent on data transfer direction. • A burst termination is not necessarily the end of a command. • The host may stop the burst to allow an ISA access through the bridge chip to be done before the command is complete. • The device may stop the burst to allow time for a head switch or seek or to force CRC to be checked before the end of the command. • CRC Checking • CRC checking is a reliability advantage for Ultra DMA. • CRC is calculated on a per-burst basis. • Both the host and the device maintain a 16-bit CRC register which is cleared at the beginning of each burst. • The Host CRC value is sent to the device at the completion of the burst for checking independent of the data transfer direction.
Protocol Changes For Ultra DMA 66 • Due to shorter cycle times, more words may be sent after DMARDY- is negated. • Previous: 0, 1, or 2 more words could be received. • Ultra 66: 0, 1, 2, or 3 more words could be received. • Host shall verify cable type as 80 conductor before setting a mode higher than 2. • Modes higher than 2 require 80 conductor cable • Devices supporting Ultra DMA modes higher than 2 shall support the device based cable detection. • Rise/fall time specification of 5 ns minimum replaced with slew rate maximum of 1.25 V/ns under same conditions.
Required IC Timing For Ultra DMA 66 • Output delay: 18 ns • From system clock edge to edge on I/O pin through 1.5V. • Across all process, temperature, voltage and loading. • Rising and falling edges. • All 16 data and output STROBE signals • Output skew: 5.5 ns • Differences in delay from system clock edge to edge on I/O pin through 1.5V between two I/O cells. • Across all process, temperature, voltage and loading • Rising and falling edges • All 16 data and output STROBE signals • Includes differences in delays due to ground bounce which directly affects time to cross 1.5V. Ground bounce during STROBE transition and DATA transitions will likely be different.
Required IC Timing For Ultra DMA 66 • Input delay: 5.5 ns • From signal edge at I/O pin through 1.5 V to core logic input of flip-flop. • Across all process, temperature, voltage and loading. • Rising and falling edges. • All 16 data and output STROBE signals • Input skew: 4.3 ns • Differences in delay from signal edge at I/O pin through 1.5 V to core logic input of flip-flop between two I/O cells. • Across all process, temperature, voltage and loading • Rising and falling edges • All 16 data and output STROBE signals • Includes skew due to the fact that V+ and V- thresholds are not at 1.5V.
Ultra DMA Timing Precautions • In order to meet all cycle and interlock timings, a 66.7 MHz Clock is practically required. • 3.5 % variation to allowed for PLLs. • If a 33Mhz clock was used in the past to meet mode 2 timings, must review control signal timings if clock is simply doubled to achieve new modes. • One 33Mhz cycle typically used to meet tENV, causes a violation if clock is doubled. • If one 33Mhz cycle used to meet tACK, causes a violation if clock is doubled.
Ultra DMA Timing Precautions • Newer motherboards have user configurable system clock frequencies from 60 to 133 MHz and higher. • PCI clock frequency may be affected by motherboard jumper settings. • The clock frequency of on board ATA ICs and PCI based ATA controller cards may be affected by the clock frequency setting of the motherboard. • Host generated Ultra DMA timings must meet the timing specification for each clock frequency configuration of that host. • Frequencies lower than 66.6Mhz may increase control signal and interlock timings beyond maximums allowed for in the standard. • Frequencies above 66.6Mhz may cause cycle times shorter than allowed for.
Ultra DMA Timing Precautions • Lower impedance and higher capacitance of the 80 conductor cable may nearly double ground bounce on some systems. • Ground bounce directly affects setup and hold timing • Differences in ground bounce between two data lines due to pattern and IC substrate impedance adds to skew between those data lines. • Differences in ground bounce during DATA and STROBE transitions adds to the skew between those lines and will reduce setup or hold times. • Ground bounce during DATA transitions will be high for some patterns. • Ground bounce during STROBE transitions will be dependent on activity of other outputs on the ATA IC. • Ground bounce directly adds to the peak voltage in a “victim” signal for DST. In modes higher than 2, this voltage should not cross 800mV.
Ultra DMA Timing Precautions • Set up and hold times are defined at the connector • Ultra DMA timings as defined at the connector account for 2ns of skew from the IC pin to the connector. Reflections and differences in loading are the primary causes of this skew. • IC timing should exceed setup and hold timings as defined at the connector by at least 2 ns over process, temperature, loading, and voltage corners. • Interlock timings are defined at the connector. • The sender must account for trace delay and input I/O cell delay for DMARDY- and output I/O cell delay and trace delay for STROBE when determining if tRP will be met under the worst case synchronization and response timing. • The receiver must account for output I/O cell and trace delay for DMARDY- and trace delay and input I/O cell delay to determine how long it must wait internally for a final STROBE edge from the sender after negating DMARDY-
Ultra DMA Timing Precautions • Setup and hold times for mode 4 have the same margin • With the 80 conductor cable, system skews are just as likely in either direction. • Best balance of setup and hold time margin in mode 4 is when the DATA transitions occur precisely at the center of the STROBE transitions. This can only be achieved by using a clock cycle for data hold time. • DO NOT use gate delays to generate data and CRC hold times. • Gate delays over process, temperature, and voltage and vary by as much as 3X causing a large variation in setup and hold times. • Since setup and hold times will not be matched under most conditions, the system will be more likely to have setup or hold time violations leading to CRC errors.
Configuration Recommendations • Follow the ATA/ATAPI standard requirement for maximum capacitance measured at the connector. • 20pF max at device, 25pF max at host connector • With typical interface IC and PCB technology, this effectively limits host trace lengths to 4-6 inches. • If the specification for maximum capacitance is not met due to long trace lengths or additional loads on the trace, Ultra DMA mode 2 on a standard 40 conductor cable may generate CRC errors due to long data settle times. Under worst conditions in this configuration, some patterns may consistently fail. • Use ATA/ATAPI specified values for pull up and pull down resistors. • Resistive values below the minimum given will increase skew and reduce timing margin and should never be used. • Resistors should be place as shown in the standard.
Configuration Recommendations • Do not exceed the 18” maximum cable length as specified in the standard. • Ideal spacing between device connectors on the 40 conductor cable is 6” independent of the cable length. • Larger spacing on either cable type increases skew when signaling to or from the middle device and should not be used. • Smaller spacing on the 40 conductor cable results in increased ringing amplitude with decreased frequency when two devices are attached. • When a 40 conductor cable is used: • A continuous electrical connection between ground on the device and on the PCB should be provided. • The cable should be routed as close to the chassis as possible. This will reduce settle time by reducing impedance of the center DATA lines during some patterns.
Configuration Recommendations • PCB Traces • Design trace impedance to be as close to the 82 ohm impedance of the 80 conductor cable to minimize reflections due to mismatch between the PCB and cable. • Keep ratio of trace spacing to height above ground plane high to control crosstalk. • Design traces to minimize differences in propagation delay between STROBE and DATA signals. • Match trace length to within +/- 0.5”. • Do not use stubs, rout on inner layers, or place pads for unused components, all of which add capacitance and affect delay. • Avoid the use of vias if possible. Use the same number of vias on all STROBE and DATA lines if vias are required. • Do not route over a break in the ground/power plane or areas with no power plane which will cause additional inductance and crosstalk.
Configuration Recommendations • Place series termination resistors as close as possible to the cable header or connector. • Choose series termination value to equalize RC delays for the STROBE and DATA lines. • If the same I/O design is used on all cells including the STROBE input, the same value termination resistor should be used on all signals. • Use sufficient ground and power pins on the interface IC to control ground bounce during simultaneous switching outputs. • I/O cells used in systems with 40 conductor cables should have rise and fall times of 5 ns or more across the full range of expected loading conditions.
Configuration Recommendations • For host systems where it is impossible to meet the ATA/ATAPI standard requirement for maximum capacitance due to a need for long traces (up to 12” in NLX and similar configurations), the additional guidelines below should be followed: • Use 80 conductor cables exclusively. If standard length 40 conductor cables are used, Ultra DMA modes higher than 1 may not be reliable. • Use 3.3V signaling. • Allow timing margin for additional propagation delays in delay-limited interlock timings. • Minimize total capacitance of traces, additional components, and I/Os pins.
80 Conductor Cable • Same connector configuration as standard 40 conductor cable. • No need for new connectors on host or devices • Interchangeable with standard cable for Modes 0-2 • Ground lines interleaved between all signal lines • 40 additional lines are all ground • No new signals • Ground lines tied together and to all 7 original ground conductors in all 3 connectors • PDIAG-:CBLID- signal conductor not connected to host, that pin of the host connector is grounded for cable detection. • Supports Cable Select with Device 0 at end connector.
Host Based Cable Detection • Already Defined in ATA/ATAPI-4. • Host connects PDIAG-:CBLID- signal to an input port. • After device 0/1 handshaking and a command has been sent to device 1 to cause it to release the PDIAG- signal, the host detects the state of CBLID-. • Host detects CBLID- below Vil = 80 conductor cable • Host detects CBLID- above Vih = 40 conductor cable • This type of cable detection is preferred over the new device based detection since it operates independent of device type. • Host shall support either one or both cable detection methods.
Device Based Cable Detection • Support • Hosts are not required to support this method, it is only an alternative to the preferred method of the host sensing CBLID-. • All devices supporting Ultra DMA modes higher than 2 shall support this alternative. • Discrete components required for support • Hosts which choose to support this alternative shall place a 0.047µF +/- 20% capacitor on the PDIAG-:CBLID- signal. • A higher value may cause failures of device 0/1 handshaking with a 40 conductor cable. • A lower value may cause a 40 conductor cable to be detected as an 80 conductor cable with this method. • Devices which support Ultra DMA modes higher than 2 shall use a 10K +/- 5% pull up resistor on PDIAG-:CBLID-. Component values chosen to allow pull up to 5V or 3.3V.
Device Based Cable Detection • When device receives an ID command, it: • Asserts PDIAG-:CBLID- (drives it low) for 30 µs minimum • Releases PDIAG-:CBLID- (shall not actively drive it) • Measures level of PDIAG-:CBLID- 2 to 13 µs after releasing it. • Device reports detected electrical level of PDIAG-:CBLID- in new ID data bit. • Bit located in ID word 93 bit 13 • PDIAG- less than Vil = 0 • PDIAG- greater than Vih = 1 • Host reads ID data and may use new bit only if host capacitor is in place and device supports Ultra DMA modes higher than 2, otherwise, it shall be ignored. • 0 = 40 conductor if both device and host support method • 1 = 80 conductor if both device and host support method
Software Overview • IDENTIFY DEVICE • Word 53 bit 2 set indicates: • Ultra DMA is supported. • Contents of word 88 is valid. • Word 88 • Upper byte indicates active Ultra DMA mode. Only one bit may be set. • Lower byte indicates Ultra DMA modes supported. Bits for all supported modes shall be set. • Word 93 bit 13 indicates sensed electrical level of PDIAG-:CBLID- during device based cable detection on devices supporting Ultra DMA modes higher than 2. • During Resets • Power on and hard resets return the device to a default non-Ultra DMA mode. • Soft resets and device resets do not change the Ultra DMA mode setting.
BIOS Responsibilities • Shall be Ultra DMA aware and enable host IC and device(s) for Ultra DMA if protocol is desired. • Shall be chipset aware to program registers of host for Ultra DMA. • Shall perform SET FEATURES command to set Ultra DMA capable devices to desired Ultra DMA mode. • Shall program Host and Device to Ultra DMA modes supported by both. • Shall determine cable type before setting Ultra DMA modes higher than 2. • Shall be system configuration aware • If GPIOs are used, shall know which GPIO is connected to PDIAG-:CBLID-. • If device based method is used, shall know that host capacitor is in place. • May be used to notify device driver of cable type. • Could write cable type to a register in the PCI register space.
Device Drivers • Drivers which don’t reprogram the host IC or devices. • Continue to work properly with Ultra DMA modes higher than 2. • CRC error reports ABRT bit in addition to ICRC bit so CRC errors are still retried. • Shall not use SET FEATURES to program DMA modes. • May check ID information before performing DMA commands. • Driver which reprogram the host IC and device. • Shall determine cable type from host IC or BIOS before setting modes higher than 2. • Driver may assume that if the BIOS has set the host and device to any mode higher than 2, then the cable has been detected by the BIOS as 80 conductor. • Shall use SET FEATURES to program device Ultra DMA mode. • Shall programming the host IC for an Ultra DMA mode supported by the device. • Should be capability of acting on ICRC error bit by retrying the command without other recovery steps.