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COSC1078 Introduction to Information Technology Lecture 12 Machine Processing

James Harland james.harland@rmit.edu.au. COSC1078 Introduction to Information Technology Lecture 12 Machine Processing. Introduction. James Harland Email: james.harland@rmit.edu.au URL: www.cs.rmit.edu.au/~jah Phone: 9925 2045 Office: 14.10.1 Consultation: Mon 4.30-5.30,

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COSC1078 Introduction to Information Technology Lecture 12 Machine Processing

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  1. Intro to IT James Harland james.harland@rmit.edu.au COSC1078 Introduction to Information TechnologyLecture 12Machine Processing

  2. Intro to IT Introduction • James Harland • Email:james.harland@rmit.edu.au • URL:www.cs.rmit.edu.au/~jah • Phone:9925 2045 • Office:14.10.1 • Consultation:Mon 4.30-5.30, • Thu 11.30-12.30 • What colour is my office door? Carpet? Chair?

  3. Intro to IT Introduction to IT 1 Introduction 2Images 3Audio 4Video WebLearnTest 1 5 Binary Representation Assignment 1 6 Data Storage 7Machine Processing 8 Operating Systems WebLearn Test 2 9 Processes Assignment 2 10 Internet 11Internet Security WebLearn Test 3 12Future of IT Assignment 3, Peer and Self Assessment

  4. Intro to IT Overview • Questions? • Assignments 1 & 2 • Machine Processing • Questions?

  5. Assignments 1& 2 Assignment 1 Currently being marked Will have marks out next week Assignment 2 Specification has been published Must be done in groups of 2 or 3 Can change groups from Assignment 1 (if you wish) Must have a blog on Blackboard Lecture 12: Machine Processing Intro to IT

  6. Intro to IT What do computers do? • Compute! • Input/Output • Processing • Memory

  7. Intro to IT Moore’s Law “Processor speed doubles about every 18 months” -- Gordon Moore, Intel co-founder, 1965 • Intended for period 1965-1975 • Held true ever since 1965! • Must end sometime …

  8. Intro to IT Moore’s Law

  9. Intro to IT Moore’s Law

  10. Intro to IT Memory • Memory differs in performance and cost • Processor is typically much faster than memory

  11. Intro to IT Memory • Arranged as a hierarchy ofcache Level 1 Level 2 Level 3 Main Memory

  12. Processing ALU MEMORY CPU BUS REGISTERS Lecture 12: Machine Processing Intro to IT

  13. Machine Instructions “Divide two numbers” Move first value from memory into register 1 Move second value from memory into register 2 If register 2 is zero, go to Step 6 Divide register 1 by register 2 & store result in register 3 Store register 3 value in memory Stop Lecture 12: Machine Processing Intro to IT

  14. Machine Instructions LOAD register 1 from memory LOAD register 2 from memory JUMP to Step 6 if register 2 is zero Divide register 1 by register 2 and store result in register 3 STORE register 3 value in memory Stop Lecture 12: Machine Processing Intro to IT

  15. Instructions in Binary? 01010100001010101010100110100010101001101001010010100011100010101010100101111001001010… 10101100 10110011 00010010 00110011 00111111 MEMORY LOAD register 1 LOAD register 2 JUMP …. STORE …. Lecture 12: Machine Processing Intro to IT

  16. One Scheme 16-bit operation codes(simple example) Operation Code (4 bits) Operand (12 bits) Represent as 4 Hexadecimal numbers (0-9,A-F) Each instruction is two bytes long Lecture 12: Machine Processing Intro to IT

  17. One Scheme 156C LOAD register 5 from memory 6C 166DLOAD register 6 from memory 6D 5056ADD register 5 & 6 & store in register 0 306ESTORE register 0 to memory 6E C000HALT .... (up to 216 = 65,536 different instructions) Lecture 12: Machine Processing Intro to IT

  18. Fetch Decode Execute FETCH Machine cycle EXECUTE DECODE Lecture 12: Machine Processing Intro to IT

  19. Two special registers Instruction register:holds current instruction Program counter:address of next instruction Fetch: Put instruction specified by program counter into instruction register Increment program counter by two Decode: Work out what to do Execute: Perform the instruction Lecture 12: Machine Processing Intro to IT

  20. Processing Address Contents A0 A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 Program Counter Instruction Register Lecture 12: Machine Processing Intro to IT

  21. Processing A0 A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 FETCH Program Counter 156C Instruction Register Lecture 12: Machine Processing Intro to IT

  22. Processing A2 A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 FETCH Program Counter 156C Instruction Register Lecture 12: Machine Processing Intro to IT

  23. Processing A2 A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 6C 2B DECODE Program Counter 156C Instruction Register Lecture 12: Machine Processing Intro to IT

  24. Processing A2 A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 6C 2B Program Counter EXEC 156C Instruction Register 5 2B Lecture 12: Machine Processing Intro to IT

  25. Processing A2 A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 FETCH Program Counter 166D Instruction Register Lecture 12: Machine Processing Intro to IT

  26. Processing A4 A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 FETCH Program Counter 166D Instruction Register Lecture 12: Machine Processing Intro to IT

  27. Processing A4 A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 DECODE Program Counter 166D Instruction Register Lecture 12: Machine Processing Intro to IT

  28. Processing A4 A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 6D FF EXEC Program Counter 166D Instruction Register 6 FF Lecture 12: Machine Processing Intro to IT

  29. Processing A6 A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 FETCH Program Counter 5056 Instruction Register Lecture 12: Machine Processing Intro to IT

  30. Processing A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 … Program Counter Instruction Register Lecture 12: Machine Processing Intro to IT

  31. Processing B4 EXEC Program Counter B258 Instruction Register Lecture 12: Machine Processing Intro to IT

  32. Processing 58 EXEC Program Counter B258 Instruction Register Lecture 12: Machine Processing Intro to IT

  33. Processing • Jump instructions change program counter • Can load any memory address into program counter (!!!) • Often use pipelining for efficiency • Fetch next instruction while executing • Processor doesn’t wait for fetch to complete • Can do more than one instruction … Lecture 11: Machine Processing Intro to IT

  34. Intro to IT Connecting devices ? ?

  35. Intro to IT Universal Serial Bus (USB)

  36. Memory-mapped I/O C4 34 FF EXEC Program Counter 3634 Instruction Register Just like writing to a memory address 6 FF Lecture 12: Machine Processing Intro to IT

  37. Direct Memory Access (DMA) Put some data in memory! OK Lecture 12: Machine Processing Intro to IT

  38. Direct Memory Access Direct Memory Access means that doesn’t have to wait for the Lecture 12: Machine Processing Intro to IT

  39. What are these? bottleneck Firewire Serial port Parallel port handshake bandwidth Lecture 12: Machine Processing Intro to IT

  40. Busy Bertie the bus … Von Neumann bottleneck Lecture 12: Machine Processing Intro to IT

  41. Intro to IT Conclusion • Work on Assignment 2 • Finish reading book!

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