CMPE 511 ON CHIP NETWORKS: A Scalable, Communication-Centric Embedded System Design Paradigm

1. CMPE 511ON CHIP NETWORKS: A Scalable, Communication-Centric Embedded System Design Paradigm Giray Kömürcü

2. OUTLINE • System On Chip (SoC) • Network On Chip (NoC) • Characteristics of NoC’s • Customization Potential for On-Chip Networks • State of the Art Research in On Chip Networks • Future Research Directions

3. System On Chip • More and more transistors available • All operations integrated on a single die • Higher level design methodologies

4. System On Chip • New architectures: • Thousands of processors • Sophisticated communication architecture • Buses are not enough • Large bus lengths -> clock skew problem • Scalable communication architecture is needed

5. Bus-Based SOC

6. Network On Chip (NoC) • Success & Scalability of Internet inspired researchers for on chip communication • Switch based networks & packet based communication • Scalability • Standardization • Reuse • Important for lowering design effort, time to market

7. NoC Features • Packets transmitted instead of words • Dedicated address lines are not necessary • Parallel transactions • Clock skew and cross talk is no concern due to routers • Structured wiring, easy routing

8. Network On Chip

9. Characteristics of NoC’s • Wiring resources: • Abundant resources for wiring • Thousands of wires at each metal layer • In non network based systems: • Hard to Predict – Hard to Avoid Cross-Coupling effects • Repeater insertion • Conservative, Slow design • More regular distribution of power distribution

10. Characteristics of NoC’s • Wiring resources: • In on chip networks: • Same length wires • Predictable delays • Predictable cross talk pattern • Non-conservative line width sizing and layout • Higher clock rates

11. Characteristics of NoC’s • Traffic Patterns: • Poisson distribution in large scale networks • More predictable in embedded systems • Pre-Scheduling increases the speed of transmissin and actual band-width

12. Characteristics of NoC’s • Heteorgeneity: • Several different algorithms on SoCs • Heterogeneous communication loads • Network architecture may be specialized to match the traffic reduces the size and power consumption

13. Characteristics of NoC’s • Power Consumption • One of the most important issues in embedded systems • NoC’s may worsen the problem • Less power for each line but more wires • More communication due to many cores • Power consumption of the interconnect is not negligible • Removal of the address lines is a plus • Data is not broadcasted as in bus systems

14. Characteristics of NoC’s • Testability • Reliability is no longer limited to critical applications • Three components are needed: • Source for generating test stimuli • Test access mechanisim to move the test data • Test scheduling strategy • Design for test strategy to minimize the volume(cost) and increase the coverage

15. Characteristics of NoC’s • Testability • NoC can be considered as a core • Is composed of identical components and interconnects each component on the system • Hierarchical structure of NoC allows test re-use • Test data can be broadcast to all identical elements • High speed interconnect testing will dominate since many lines in the system • Presence of communication protocol complicates testing • Timing tests are important since clock boundaries of cores are in the network interface

16. Characteristics of NoC’s • Limitations • Memory access between IP cores and memory cores is a performance bottleneck • No standardization • Customization may boost the performance • Hard to achieve large scale reusability of the communication backbone • Hard to create design independent communication IP Cores • Adoption of Network on Chips will be slow • Designers are not expert on the network concept • CAD tools should be developed

17. Customization Potential for On-Chip Networks • Large scale networks have to be strictly standardized to serve each client • Minor issue in on chip networks • IP core can be freely designed to fit any NoC • If standardized, IP cores from different vendors can be used • Customization of networks may lead best performance, area and power consumption

18. Architectural Customization • Network topologies can be characterized by: • Number of links connecting a node to others • Maximum distnance between any two nodes • Regularity • Symmetry • Heterogenity of computation should be reflected in the NoC to prevent over design • Buffer Size • Number of Virtual channels

19. Architectural Customization

20. Protocol Customization • Communication Protocols: Rules and Methods required for transfer between IP’s • Handshaking via request & acknowledge • More complex protocols in NoC’s • Application Specific customization of protocols can provide huge power and performance benefits • Packet size and Routing are two characteristics of protocol customization

21. Protocol Customization • Routing: • Path origin to the destination • Connectivity • Adaptivity • Deadlock and livelock freedom • Fault tolerance • Is broadcasting required

22. Protocol Customization • Packet size: • Finding the optimum is crucial for optimum use of network resources • Depends on the characteristics of the application (data or control) • Too small packets have overhead to reunite • Too big packets may block traffic for long time • Should be chosen according to buffer size

23. Protocol Customization

24. Customization for Quality of Service • Performane of the combination must be validated • Behaviour of NoC and IP Cores should be abstracted to see service requirements • Retransmission or error correction • Error correction quaranties minimum BW • If Data is not accepted by the IP data is lost if not enough buffers • A clear, service level specification of the NoC services is necessary • Flow control is essential • NoCs must implement a resource management strategy to allocate BW and notifies the IP

25. Customization in HW/SW Trade Off • Router-Switch may be a part of local processor • Routing and arbitration algorithms may be assumed by the local processor • Virtual channels may be managed by the local processor • Local Memory may be used instead of buffers

26. State of the Art Research in On Chip Networks • Architectural Issues: • Adopting buffers efficiently to trade off performance and cost • Packetization of data • Designing router architecture to trade of cost and efficiency • Complex architectures using NoC’s

27. Power Energy Issues • Estimating a routers power consumption • Sthocastic traffic models for transition activity, packet arrival and departure events • Simulation based framework • Bit level energy estimation of routers • Interconnect models to compute power at system level

28. Simulation Issues • Crucial to estimate performance before implementation • Protocol and topology simulations • Accurate vs fast simulation

29. Future Research Directions • Few concrete implementations for complex NoCs • Standardization • Cycle accurate simulation is not appropriate since more than one proccessing units • Cycle approximate simulations may develop • Communication centric simulation is needed • Hierarchical architectures to build efficient NoCs with hundreds of non uniform cores • Cross talk problem

30. CONCLUSION • Communication architectures on chip become bottleneck with more and more transistors • Network On Chip’s are a good solution for SoCs in the billion transistor era • Packets transmitted instead of words • Dedicated address lines are not necessary • Parallel transactions • Clock skew and cross talk is no concern due to routers • Structured wiring, easy routing • Customization of NoC’s gives the oppotunity to achieve high performance in SoC’s

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