Based on slides from D. Patterson and www-inst.eecs.berkeley/~cs152/

1. COM 249 – Computer Organization andAssembly LanguageChapter 2 Instructions:Language of the Computer Based on slides from D. Patterson and www-inst.eecs.berkeley.edu/~cs152/ Modified by S. J. Fritz Spring 2009 (1)

2. Introduction • Words of a computer’s language are called its instructions • Its vocabulary is itsinstruction set. • Goal: • Find a language that makes it easy to build the hardware and the compiler, • while maximizing performance and minimizing cost Modified by S. J. Fritz Spring 2009 (2)

3. Instruction Set §2.1 Introduction • Different computers have different instruction sets • But with many aspects in common • Early computers had very simple instruction sets • Simplified implementation • Many modern computers also have simple instruction sets Modified by S. J. Fritz Spring 2009 (3)

4. Instruction Set Architecture • Early trend was to add more and more instructions to new CPUs to do elaborate operations • VAX architecture had an instruction to multiply polynomials! • RISC philosophy (Cocke IBM, Patterson, Hennessy,1980s)–Reduced Instruction Set Computing (RISC) • Keep the instruction set small and simple, makes it easier to build fast hardware. • Let software do complicated operations by composing simpler ones. Modified by S. J. Fritz Spring 2009 (4)

5. The MIPS Instruction Set • Stored program concept- instructions and data are stored as numbers. • MIPS Instruction Set is used as the example throughout the book • Stanford MIPS commercialized by MIPS Technologies (www.mips.com) • Large share of embedded core market • Applications in consumer electronics, network/storage equipment, cameras, printers, … • Typical of many modern ISAs • See MIPS Reference Data tear-out card, and Appendixes B and E Modified by S. J. Fritz Spring 2009 (5)

6. MIPS Architecture • MIPS – semiconductor company that built one of the first commercial RISC architectures • We will study the MIPS architecture in some detail in this class • Why MIPS instead of Intel 80x86? • MIPS is simple, elegant. Don’t want to get bogged down in gritty details. • MIPS widely used in embedded apps, x86 little used in embedded, and more embedded computers than PCs Modified by S. J. Fritz Spring 2009 (6)

7. Review: Instruction Set Design software instruction set hardware Which is easier to change? Modified by S. J. Fritz Spring 2009 (7)

8. Stored Program Computer • Basic Principles • Use of instructions that are indistinguishable from numbers • Use of alterable memory for programs • Demands balance among number of instructions, the number of clock cycles needed by an instruction and the speed of the clock. Modified by S. J. Fritz Spring 2009 (8)

9. Overview of Design Principles 1. Simplicity favors regularity • keep all instructions a single size • require three register operands for arithmetic • keep register fields in same place in each instruction • regularity makes implementation simpler • simplicity enables higher performance at lower cost 2. Smaller is faster • the reason that MIPS has 32 registers rather than many more Modified by S. J. Fritz Spring 2009 (9)

10. Overview of Design Principles 3.Make the common case fast • PC-relative addressing for conditional branch • immediate addressing for constant operands 4.Good design demands good compromises • compromise between larger addresses and keeping instructions same length Modified by S. J. Fritz Spring 2009 (10)

11. MIPS Instructions • Design Principle 1: Simplicity favors regularity • The MIPS assembly language instruction add a, b, c means a = b + c • Each line represents one instruction • Each instruction has exactly 3 operands for simplicity • There is one operation per MIPS instruction • Instructions are related to operations (=, +, -, *, /) in C or Java §2.2 Operations of the Computer Hardware Modified by S. J. Fritz Spring 2009 (11)

12. Arithmetic Operations- Addition • The MIPS assembly language instruction add a, b, c means a = b+c • This sequence adds four variables (a=b+c+d+e) add a, b, c # the sum of b and c is placed in a add a, a, d # the sum of b,c, and d is now in a add a, a, e # the sum of b,c,d and e is now in a • Notice that it takes 3 instructions to add four variables Modified by S. J. Fritz Spring 2009 (12)

13. MIPS Addition and Subtraction • Syntax of Instructions: 1 2,3,4 where: 1)operation by name 2) operand getting result (“destination”) 3) 1st operand for operation (“source1”) 4) 2nd operand for operation (“source2”) • Syntax is rigid: • 1 operator, 3 operands • Why? Keep Hardware simple via regularity Modified by S. J. Fritz Spring 2009 (13)

14. MIPS Addition and Subtraction of Integers • Addition in Assembly • Example: add $s0,$s1,$s2 (in MIPS) Equivalent to: a = b + c (in C/Java) where MIPS registers $s0,$s1,$s2 are associated with C variables a, b, c • Subtraction in Assembly • Example: sub $s3,$s4,$s5 (in MIPS) Equivalent to: d = e - f (in C) where MIPS registers $s3,$s4,$s5 are associated with C variables d, e, f Modified by S. J. Fritz Spring 2009 (14)

15. Addition and Subtraction • How would MIPS do this C/Java statement? a = b + c + d - e; • Break into multiple instructions add $t0, $s1, $s2 # temp = b + c add $t0, $t0, $s3 # temp = temp + d sub $s0, $t0, $s4 # a = temp - e • Notice: A single line of C or Java may break up into several lines of MIPS. Everything after the hash mark- # - on each line is ignored (comments) Modified by S. J. Fritz Spring 2009 (15)

16. Compiling C into MIPS • How do we do this? • C code: f = (g + h) - (i + j); • Use intermediate temporary registers: • Compiled MIPS pseudocode: add t0, g, h # temp t0 = g + hadd t1, i, j # temp t1 = i + jsub f, t0, t1 # f = t0 - t1 • Comments are to the right of the # • Each line contains at most one instruction Modified by S. J. Fritz Spring 2009 (16)

17. C, Java Variables vs. Registers • In C (and most High Level Languages) variables are declared first and given a type • Example: int fahr, celsius; char a, b, c, d, e; • Each variable can ONLY represent a value of the declared type (cannot mix and match int and char variables). • In Assembly Language, the registers have no type; operation determines how register contents are treated Modified by S. J. Fritz Spring 2009 (17)

18. Operands of the Computer Hardware • Operands of arithmetic instructions must be from a limited number of special memory locations called registers • Size of a MIPS register is32 bits- called aword (although there is a 64 bit version). • Major difference between variables in programming language (unlimited) andregisters is the limited number of registers- typically 32 in MIPS. §2.3 Operands of the Computer Hardware Modified by S. J. Fritz Spring 2009 (18)

19. Operands of the Computer Hardware • Design Principle 2: Smaller is faster • Very large number of registers may increase clock cycle time because it takes electronic signals longer to travel farther. • Using more than 32 registers would require a different instruction format. • MIPS register convention is to use two character names following a dollar sign: $s0, $s1… for variables $t0, $t1… for temporary locations $a0, $a1…for arguments Modified by S. J. Fritz Spring 2009 (19)

20. Compiling C into MIPS Using Registers • C code: (similar to previous example) f = (g + h) - (i + j); • where f, g, h, i, j are assigned to registers $s0, $s1, $s2, $s3 and $s4 respectively: • Compiled MIPS code: add $t0,$s1,$S2 #register $t0 = g + hadd $t1,$s3,$s4 #register $t1 = i + jsub $S0,$t0,$t1 #f gets $t0 - $t1 • Variables have been replaced with registers Modified by S. J. Fritz Spring 2009 (20)

21. Register Operands • Arithmetic instructions use registeroperands • MIPS has a 32 × 32-bit register file (32 registers, each 32 bits) • Use for frequently accessed data • Numbered 0 to 31 • 32-bit data called a “word” Modified by S. J. Fritz Spring 2009 (21)

22. Memory Operands • Programming Languages have both simple variables and complex data structures. • How can we handle large data structures with just a few registers? • Data structures are kept in memory. • MIPS includes instructions to transfer data between memory and registers. • Data transfer instructions ( load, store) Modified by S. J. Fritz Spring 2009 (22)

23. Memory Operands • Data transfer Instruction • load copies data from memory to register • lw - load word • Format opcode register , constant (register) memory address • Syntax lw $t0, 8 ($s3) offset base address Modified by S. J. Fritz Spring 2009 (23)

24. Memory Addressing ° Since 1980 almost every machine uses addresses to the level of 8-bits ( byte) 2 questions for design of Instruction Set Architecture: • Since we could read a 32-bit word as • four loads of bytes from sequential byte addresses • or as one load word from a single byte address, How do byte addresses map onto words? Can a word be placed on any byte boundary? Modified by S. J. Fritz Spring 2009 (24)

25. Addressing Objects: Alignment • Since 8-bit bytes are useful, most architectures address individual bytes. • Address of a word matches the address of one of the four bytes in the word • Addresses of sequential words differ by 4 bytes • MIPS words must start at addresses that are multiples of 4 - called alignment restriction Modified by S. J. Fritz Spring 2009 (25)

26. Memory Operands • Arithmetic operations occur on registers • More complex data structures (arrays and structures) are kept in memory • MIPS must include instructions that transfer data between memory and registers (called data transfer instructions) • To access a word in memory, the instruction must include the memory address. Modified by S. J. Fritz Spring 2009 (26)

27. Memory Operands • Main memory used for composite data • Arrays, structures, dynamic data • To apply arithmetic operations • Load values from memory into registers • Store result from register to memory • Memory is byte addressed • Each address identifies an 8-bit byte • Words are aligned in memory • Address must be a multiple of 4 • MIPS is Big Endian • Most-significant byte at least address of a word • c.f. Little Endian: least-significant byte at least address Modified by S. J. Fritz Spring 2009 (27)

28. Addressing Objects: Endianess • Computers are grouped into those that use: • the address of the leftmost or “big end byte” as the word address • and those that use the “little end” or rightmost byte • MIPS is in the BIG Endian group Modified by S. J. Fritz Spring 2009 (28)

29. Addressing Objects: “Endianess” and Alignment • Big Endian: address of most significant :IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA • Little Endian: address of least significant: Intel 80x86, DEC Vax, DEC Alpha (Windows NT) little endian byte 0 3 2 1 0 msb lsb 0 1 2 3 0 1 2 3 Aligned big endian byte 0 Alignment: require that objects fall on address that is multiple of their size. Not Aligned Modified by S. J. Fritz Spring 2009 (29)

30. Big Endian • "Big Endian" means that the high-order (most significant) byte of the number is stored in memory at the lowest address, and the low-order (least significant) byte at the highest address. (The “big end” comes first.) • A LongInt, would then be stored as: Base Address+0 Byte3 Big Endian Base Address+1 Byte2 Base Address+2 Byte1 Base Address+3 Byte0 Little Endian • Motorola processors (those used in Mac's) and mainframes use "Big Endian" byte order. • http://www.cs.umass.edu/~Verts/cs32/endian.html A B C D Modified by S. J. Fritz Spring 2009 (30)

31. Little Endian • "Little Endian" means that the low-order byte of the number is stored in memory at the lowest address, and the high-order byte at the highest address. (The little end comes first.) • A 4 byte LongInt Byte3 Byte2 Byte1 Byte0 will be arranged in memory as follows: Base Address+0 Byte0 Base Address+1 Byte1 Base Address+2 Byte2 Base Address+3 Byte3 • Intel processors (those used in PC's) use "Little Endian" byte order. • http://www.cs.umass.edu/~Verts/cs32/endian.html Modified by S. J. Fritz Spring 2009 (31)

32. Big Endian and Little Endian • To represent the value 1025 (as a 4 byte integer): 00000000 00000000 0000010000000001 Address Big-Endian Little-Endian If UNIX were stored as 2 two-byte words then in a Big-Endian systems, it would be stored as UNIX; in a Little-Endian system, it would be stored as NUXI. (See http://www.webopedia.com/TERM/B/big_endian.html ) Modified by S. J. Fritz Spring 2009 (32)

33. Big and Little Endian • Both have advantages and disadvantages • In "Big Endian" form, by having the high-order byte come first, you can test whether the number is positive or negative by looking at the byte at offset zero. • In "Little Endian" form, assembly language instructions for picking up a 1, 2, 4, or longer byte number proceed in exactly the same way for all formats and multiple precision math routines are correspondingly easy to write. • http://www.cs.umass.edu/~Verts/cs32/endian.html Modified by S. J. Fritz Spring 2009 (33)

34. MIPS I Registers • Programmable storage • 232 x bytes of memory(r0-31) • 32 x 32-bit • General Purpose Registers GPRs (R0 = 0) 32 bits “wide” Modified by S. J. Fritz Spring 2009 (34)

35. 100 10 101 1 Memory Addresses and Contents 3 2 1 0 Address Data Processor Memory The address of the third data element is 2 and the contents of Memory[2] is 10. Modified by S. J. Fritz Spring 2009 (35)

36. Registers vs. Memory • Registers are faster to access than memory • Operating on memory data requires loads and stores • More instructions to be executed • Compiler must use registers for variables as much as possible • Only spill to memory for less frequently used variables • Register optimization is important! Modified by S. J. Fritz Spring 2009 (36)

37. Arrays and Data Structures • C and Java variables map onto registers; what about large data structures like arrays? • 1 of the 5 components of a computer - the memory- contains such data structures • But MIPS arithmetic instructions only operate on registers, never directly on memory. • Data transfer instructions transfer data between registers and memory: • Memory to register (Load) • Register to memory (Store) Modified by S. J. Fritz Spring 2009 (37)

38. Store (to) Load (from) Anatomy: 5 components of any Computer Registers are in the datapath of the processor; if operands are in memory, we must transfer them to the processor to operate on them, and then transfer back to memory when done. Personal Computer Computer Processor Memory Devices Input Control (“brain”) Datapath Registers Output These are “data transfer” instructions… Modified by S. J. Fritz Spring 2009 (38)

39. Data Transfer: Memory to Registers • To transfer a word of data, we need to specify two things: • Register: specify this by # ($0 - $31) or symbolic name ($s0,…, $t0, …) • Memory address: more difficult • Think of memory as a single one-dimensional array, so we can address it simply by supplying a pointer to a memory address. • Other times, we want to be able to offset from this pointer. • Remember: “Load FROM memory” Modified by S. J. Fritz Spring 2009 (39)

40. Data Transfer: Memory to Registers • To specify a memory address to copy from, specify two things: • A register containing a pointer to memory • A numerical offset (in bytes) • The desired memory address is the sum of these two values. • Example: 8($t0) • specifies the memory address pointed to by the value in $t0, plus 8 bytes Modified by S. J. Fritz Spring 2009 (40)

41. Data Transfer: Memory to Register • Load Instruction Syntax: 1 2, 3(4) lw $t0,12($s0) where 1) operation name 2) register that will receive value 3) numerical offsetin bytes 4)register containing pointer to memory • MIPS Instruction Name: • lw (meaning Load Word, so 32 bits or one word are loaded at a time) Modified by S. J. Fritz Spring 2009 (41)

42. Data Transfer: Memory to Register Data flow Example: lw $t0,12($s0) This instruction will take the pointer in $s0, add 12 bytes to it, and then load the value from the memory pointed to by this calculated sum into register $t0 • Notes: • $s0 is called the base register • 12 is called the offset • offset is generally used in accessing elements of array or structure: base register points to beginning of array or structure Modified by S. J. Fritz Spring 2009 (42)

43. Data Transfer: Register to Memory • Also want to store from register into memory • Store instruction syntax is identical to Load’s • MIPS Instruction Name: sw (meaning Store Word, so 32 bits or one word are loaded at a time) • Example: sw $t0,12($s0) This instruction will take the pointer in $s0, add 12 bytes to it, and then store the value from register $t0 into that memory address • Remember: “ Store INTO memory” Data flow Modified by S. J. Fritz Spring 2009 (43)

44. Data Transfer Instructions- Load • Load copies data from memory to a register- in MIPS lw or load word • Format – operation name followed by the register to be loaded, then a constant and register used to access memory • Sum of the constant portion of the instruction and the constants of the second registers forms the memory address Modified by S. J. Fritz Spring 2009 (44)

45. Data Transfer Instructions- Load • Assume A is an array of 100 words, with a starting or base address in $s3 • Let g, h be variables associated with $s1,$s2 • C Assignment Statement: g = h + A[8]; • Compiling to MIPS with operand in Memory • First transfer A[8] to a register: (use load word - lw) lw $t0, 8($s3) #Temp register $t0 gets A[8] add $s1,$s2,$t0 # g = h + A[8] • The constant 8 is the offset and the register ($s3) added to form the address is called the base register. Modified by S. J. Fritz Spring 2009 (45)

46. 100 10 101 1 Actual MIPS Memory Addresses and Contents 12 8 4 0 Address Data Processor Memory Since MIPS addresses each byte, word addresses are multiples of 4; there are 4 bytes in a word. Byte address of third word is 8. Modified by S. J. Fritz Spring 2009 (46)

47. Data Transfer Instructions- Store • Instruction complementary to load is called store, or store word – sw- which copies data from a register to memory • Format similar to load instruction: name of operation, followed by the register to be stored, then offset to select the element, and finally the base register. Modified by S. J. Fritz Spring 2009 (47)

48. Data Transfer Instructions- Store • Assume variable h is associated with register $s2 • Base address of array A is in $s3. • C code: A[12] = h + A[8]; • MIPS code: lw $t0, 32($s3) # temp reg $t0 gets A[8] add $t0, $s2, $t0 # temp reg $t0 gets h + A[8] sw $t0, 48($s3) # stores h + A[8] into A[12] Modified by S. J. Fritz Spring 2009 (48)

49. MIPS Memory Addressing • Most architectures addresses individual bytes, therefore the address of a word matches the address of one of the 4 bytes within the word. • Addresses of sequential wordsdiffer by 4. • In MIPS, words must start at addresses that are multiples of 4.- called assignment restriction. • Remember MIPS is “big endian” • Byte addressing affects the array index. • Offset to be added to the base register $s3 (in previous example) must be (4 x 8) or 32. Modified by S. J. Fritz Spring 2009 (49)

50. Constants or Immediate Operands • Design Principle 3: Make the common case FAST • Constants occur frequently and by including constants in arithmetic instructions, they are faster than if the constants were loaded from memory: lw $t0, AddrContant4($s1) # t0 = constant 4 • To add 4 to register 3 use add immediate (addi): addi $s3, $s3, 4 # $s3 = $s3+4 • Since MIPS supports negative constants, there is no need for a subtract immediate instruction. Modified by S. J. Fritz Spring 2009 (50)