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Introduction

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  1. Introduction The input network of the power amplifier will be designed in the example. The network synthesized will be expanded to allow for biasing of the transistor gate. Some of the stubs in the network will be replaced with stepped main-line sections. A thin-film resistor will also be added to the network to stabilize the transistor. The performance will be restored by optimizing the network. The discontinuity effects of the steps will also be reduced by adding extra steps in the network. The effects of these steps on the performance will also be eliminated by optimization.

  2. The amplifier as designed previously. The length of the input line selected has been increased to allow the matching network to be synthesized to start with a shunt element.

  3. The specifications for the required matching network will be set up by using one of the wizards provided in a Schematic View.

  4. The Impedance-Matching Wizard shown will be selected.

  5. The network required will be inserted to the right of the selected component.

  6. The position at which the network will be inserted is high-lighted.

  7. The Impedance-Matching Wizard has been launched.

  8. The passband can be changed on this page.

  9. A default name and title were assigned to the matching problem.

  10. The default option to control the gain/VSWRs associated with the input network will be used.

  11. The impedances to be matched are listed in the table.

  12. The option to display the impedances to be matched graphically was selected.

  13. The steps provided by the wizard were completed. The Impedance-Matching Module will be launched next.

  14. The impedance-matching document has been opened. The original circuit file is still open too.

  15. The option to synthesize non-commensurate microstrip networks has been selected.

  16. The terminations page will be selected in order to change the gain specified.

  17. The terminations and the gain specified. Note that the default gain values were set to level the gain response of the amplifier.

  18. The Gain Slope Command has been selected to change all the gain values to 0 dB (best match instead of lowest gain ripple).

  19. The gain values were adjusted to 0 dB.

  20. Some of the Topology Settings will be changed.

  21. Five-element lowpass solutions, with the first element (load side) shunt, will be synthesized.

  22. The default settings for Gain Window and the Q-range are displayed.

  23. The lumped element values will not be constrained.

  24. The Distributed Networks Wizard will be launched.

  25. The first page of the wizard is displayed.

  26. The same substrate will be used.

  27. The specifications for the vias allowed. By setting a large step size only one via size is allowed.

  28. Double stubs will be allowed in the networks to be synthesized.

  29. The line widths and the stub separation to be used.

  30. A rendering of the specifications made is displayed. The blue box shown represents the height of the substrate.

  31. The parasitics associated with the junctions in the networks to be synthesized. The range allowed for the main-line should also be checked.

  32. The last page of the wizard is displayed.

  33. The changes made are saved.

  34. The Synthesis Command will be selected.

  35. The best solutions obtained with the specifications made. Note that Q3 is outside the search range specified (-4.4, 4.4).

  36. The artwork of the first solution.

  37. The command to display the next solution will be selected.

  38. The second solution obtained.

  39. The third solution obtained.

  40. The Q-range will be extended to see if better solutions are available.

  41. The Search Parameters Command will be selected.

  42. The Quick Edit feature is used to increase the search range.

  43. The new Q-range.

  44. The Synthesis Command will be selected again.

  45. The best solution obtained this time. Q3 is higher than before and the solution is more sensitive to component changes.

  46. The second solution obtained.

  47. The third solution obtained.

  48. The artwork of the second solution will be displayed.

  49. The artwork of the second solution.

  50. The second solution will be exported to circuit file.