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Scan Chain Reorder

Scan Chain Reorder. Sying-Jyan Wang Department of Computer Science National Chung-Hsing University. Outline. Overview Scan chain order: does it matter? Cluster-based reordering for low-power BIST Experimental results Future work. Outline. ■ Overview Scan chain order: does it matter?

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Scan Chain Reorder

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  1. Scan Chain Reorder Sying-Jyan Wang Department of Computer Science National Chung-Hsing University NCHUCS

  2. Outline • Overview • Scan chain order: does it matter? • Cluster-based reordering for low-power BIST • Experimental results • Future work NCHUCS

  3. Outline ■Overview • Scan chain order: does it matter? • Cluster-based reordering for low-power BIST • Experimental results • Future work NCHUCS

  4. Digital Testing • To detect manufacturing defects • Apply test patterns and observe output responses • Test patterns generated for targeted fault models NCHUCS

  5. Scenario for Manufacture Test TEST VECTORS … MANUFACTURED CIRCUIT … CIRCUIT RESPONSE CORRECT RESPONSES COMPARATOR PASS/FAIL NCHUCS

  6. Scan Test (1) • A structural design-for-testability technique • Storage elements are not directly accessible • Scan test provides an easy way for test access • Apply test patterns to circuit under test (CUT) • Read output responses from CUT NCHUCS

  7. Scan Test (2) • Sequential circuit • FFs are neither controllable nor observable Combinational Logic Primary Input Primary Output F F NCHUCS

  8. Scan Test (3) • Normal signal path: parallel load Combinational Logic Primary Input Primary Output F F NCHUCS

  9. Scan Test (4) • In scan mode: a shift register Combinational Logic Primary Input Primary Output Scan out (SO) F F Scan in (SI) NCHUCS

  10. Scan Test (5) • To enable scan test • Each scan cell has two inputs • Normal input • Scan input • All scan cells are connected into a shift register (scan chain) • Turn a sequential test into a combinational one • Apply test patterns directly • Observe test results directly NCHUCS

  11. Scan Chain • Normally constructed when placement and routing are done • The order does not matter • Find out the shortest scan chain order • Traveling salesman problem (TSP) • Asymmetric TSP (ATSP) • SI and SO of a scan cell are not at the same location • NP-complete NCHUCS

  12. Outline • Overview ■Scan chain order: does it matter? • Cluster-based reordering for low-power BIST • Experimental results • Future work NCHUCS

  13. 1 1 1 1 1 1 0 0 0 0 0 0 Scan Test for Stuck-at Faults • Order does not matter • As long as we can scan in test patterns and scan out test responses CUT 1010 1100 NCHUCS

  14. Minimum Wirelength Routing • Use a TSP/ATSP solver • Slow • Wirelength can be 10x with random order NCHUCS

  15. 1 1 1 1 0 0 0 0 1010 1100 Low-Power Testing • A great concern in recent years • Need to reduce signal transitions • The source of dynamic power in CMOS • Usually the dominant factor • Reorder scan chain to reduce switching activity 1 transition only 3 transitions NCHUCS

  16. Delay Testing (1) • Require two-pattern tests • First pattern: initialization • Second pattern: launch transition • Delay test with simple scan chain • Broadside • The output response of the 1st pattern are captured in the scan chain and become the 2nd pattern • Skewed load • The 2nd pattern is the result of 1-bit shift of the 1st pattern NCHUCS

  17. Delay Test (2) • Broadside test • Eg. Apply v1=(1010), v2=(0100) Combinational Logic Primary Input Primary Output 0 1 0 0 F F 1 0 1 0 0 1 0 0 NCHUCS

  18. 1 1 1 1 0 0 0 0 1100 1010 0 1 1 0 Delay Test (3) • Skewed load • Not all test pairs possible • 2n2n possible 2-pattern combinations • Only 22n possible with single scan chain • Reorder scan chain to achieve higher fault coverage 0110 NOT POSSIBLE!! NCHUCS

  19. Hold Time Violation • Not enough propagation delay between adjacent flip-flops in a sequential circuit • Double latching • Possible solution • Reorder scan cells to introduce extra delay NCHUCS

  20. Outline • Overview • Scan chain order: does it matter? ■Cluster-based reordering for lower-power BIST • Experimental results • Future work NCHUCS

  21. Overview • Goal: Reduce BIST power • Approach • Include a smoother to reduce switching activity in test pattern generator (TPG) • Use scan chain reordering to recover lost fault coverage • Simple reordering algorithm • Wirelength should not increase too much NCHUCS

  22. Overall Architecture Single scan chain PRPG Smoother Internal scan chain ORA TPG CUT multiple scan chain P R P G P h a s e s h i f t e r Smoother Internal scan chain 1 O R A Smoother Internal scan chain 2 . . . . . . . . Smoother Internal scan chain k NCHUCS

  23. . . . 1/1 1/0 Sn/2–1 Sn–1 1/1 1/0 0/1 1/1 0/0 1/0 . . . 0/1 1/1 0/0 1/0 0/1 0/0 1/0 1/1 Sn/2 S0 0/1 0/0 1/0 0/1 1/1 0/0 1/1 1/0 0/1 0/0 1/0 1/1 S1 S1 S3 S3 S5 S7 S4 0/1 0/0 1/0 1/1 S2 S6 0/0 S0 S0 S2 0/0 0/1 0/1 Smoother 4-state (2bit) smoother 8-state (3bit) smoother n-state smoother NCHUCS

  24. u  q C Divide-by-n/2 Up-Down Counter T in  q d C0 A Simple Implementation of then-state smother NCHUCS

  25. Estimation of Power Reduction • Probability of signal transition of an n-state smoother • Compute from Markov chain model • Estimation of dynamic power • 2-bit (4-state ) smoother: 1/3 • 3-bit (8-state) smoother: 1/10 NCHUCS

  26. Reorder scan chain: Required test cube: xxxxx01xxxxxxxx xxxxx0x1xxxxxxx PRPG 2-bit smoother 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 3-bit smoother 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Fault Coverage • Smoothed patterns are less random • May create repeated patterns and reduce fault coverage • 1 0 1 0 1 0 1 0 0 1 0 1 1 0 0 MATCH 2-bit smoother NO MATCH! NCHUCS

  27. Cluster-Based Scan Chain Reorder • Layout surface divided into clusters • Reorder limited in single cluster • Snake-like global routing Multiple scan chains Single scan chain NCHUCS

  28. 256 clusters Silicon Ensemble 1 cluster Example • Routing s15850 • 611 scan cells NCHUCS

  29. Optimal Cluster Size • Is there an optimal cluster size? • Observation • Large clusters--long vertical connection • Small clusters--more horizontal crossings • How to find optimal cluster size • Find an expression of total wirelength • Take its derivative with respect to cluster size c NCHUCS

  30. CL2 CL1 sc4 sc1 sc5 sc2 sc3 CL1 sc1 sc2 sc3 Estimate Wirelength in a Cluster (1) • Two types of order • Random order • Sorted according to x-cooridnate NCHUCS

  31. w h (0,0) sc1(X1, Y1) sc2(X2, Y2) Estimate Wirelength in a Cluster (2) • How to estimate the distance between two cells • Manhattan distance • Horizontal and vertical distances are independent • Assuming cells are randomly distributed NCHUCS

  32. Estimate Wirelength in a Cluster (3) • Expected vertical distance between two cells • Expected horizontal distance between two cells • Random order: w/3 • Sorted order • Summation of all horizontal distances: w NCHUCS

  33. Estimate Wirelength in a Cluster (4) • Random order • N: # cells, c2: #clusters • Sorted order NCHUCS

  34. Optimal Number of Clusters (1) • Random order • Assuming HW, N/c2 1 • Sorted order • Assuming HW, N/c2 3 NCHUCS

  35. Optimal Number of Clusters (2) • Reordering algorithm • Larger clusters give better results • Almost no reordering when N/c2 1 • Choose sorted order if no special order is preferred • Optimal cluster size 2  N/c2  3 NCHUCS

  36. Outline • Overview • Scan chain order: does it matter? • Cluster-based reordering for low-power BIST ■Experimental results • Future work NCHUCS

  37. Experimental Results—Wire Length (1) • 2-bit smoother NCHUCS

  38. Experimental Results—Wire Length (2) • 3-bit smoother NCHUCS

  39. Experimental Results—Fault Coverage (1) • 2-bit smoother NCHUCS

  40. Experimental Results—Fault Coverage (2) • 3-bit smoother NCHUCS

  41. Optimal Number of Cells per Cluster SE: Silicon Ensemble NCHUCS

  42. Test Efficienct NCHUCS

  43. Comparison of Average Power *Full scan; : only state vectors are scanned NCHUCS

  44. Peak Power • Capture-cycle power is not reduced • Still provide some improvement NCHUCS

  45. Outline • Overview • Scan chain order: does it matter? • Cluster-based reordering for low-power BIST • Experimental results ■Future work NCHUCS

  46. Conclusion • Scan chain reorder is very effect to deal with • Test power • Scan-based delay test • Fault coverage in BIST • Need to consider • Physical design infromation NCHUCS

  47. Future Work • Fast reordering algorithm for delay test • Integrate reordering algorithm, considering • Test power • Delay test coverage • Wire length • Other issues NCHUCS

  48. THE END Thank You! NCHUCS

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