Synchron’08

1. SoC Conception Methodology Jean-François LE TALLEC INRIA SOP lab, EPI AOSTE ScaleoChip Company Synchron’08

2. 2 • System on Chip & conception • Early experiment & result • Next

3. 3 System on Chip • What’s a SoC ? • Piece of software • IP software for modularity IP software IP software IP software

4. 4 System on Chip • What’s a SoC ? • Piece of software & hardware • IP software for modularity • IP hardware for fast execution IP software IP hardware IP software IP hardware IP hardware IP software

5. 5 System on Chip • What’s a SoC ? • Piece of software & hardware & interconnect • IP software for modularity • IP hardware for fast execution • interconnect IP software IP hardware IP software IP software IP software IP hardware IP hardware IP software IP software

6. 6 System on Chip • What’s a SoC ? • Piece of software & hardware & interconnect • IP software for modularity • IP hardware for fast execution • interconnect System Chip IP software IP hardware IP software IP software IP software IP hardware IP hardware IP software IP software

7. 7 SoC conception Usual methodology up to now: full design software Spec Final product

8. 8 SoC conception Usual methodology up to now: full design software Spec Final product ScaleoChip methodology: Real design FPGA pre-design Spec Final product software • Speed up SoC conception • More tolerant to bug

9. 9 Designing problems • Problems up to now • Hardware needed to test software • Interconnect Dimensioning • HW/SW partitioning

10. 10 Designing problems • Problems up to now • Hardware needed to test software • Interconnect Dimensioning • HW/SW partitioning • Potential solution • Physical one : ScaleoChip • Virtual one : virtual platform • ARM SoC designer (SystemC inside) • Virtutech • Vast • Coware • Cofluent

11. 11 SystemC • C++ library • Aiming to describe HW & SW • Different level of description • PV to RTL • Simulation & event based • wait on event or on time • Hierarchical description • modules, ports, signals • Process type • sc_method • sc_thread

12. 12 Early experiments Encoding of a realistic case study of an IP component : Proprietary Flash Controller from Verilog to SystemC (our running example) AHB Bus AHB2APB Bridge Cortex M3 Flash A Flash Controller Flash B

13. 13 Early experiments • Several steps • replace Verilog version by SystemC-RTL rewritting • verify behavior preservation • plug in a larger system description for RTL simulation

14. 14 Early experiments • Several steps • replace Verilog version by SystemC-RTL rewritting • verify behavior preservation • plug in a larger system description for RTL simulation • Results • Time consuming • Behavior can be maintained • Simulation consumes 11% more than original one

15. 15 Early experiments • Several steps • replace Verilog version by SystemC-RTL rewritting • verify behavior preservation • plug in a larger system description for RTL simulation • Results • Time consuming • Behavior can be maintained • Simulation consumes 11% more than original one • => Don’t really scale up

16. 16 Some other results • SystemC scheduler Parallelism emulation • method re-activation during delta-cycle til stabilization • => event partially ordered may be more efficient • Assume static cycle will stabilize • Known at simulation time if scenario is well chosen

17. 17 Next • Flash Controller • control oriented • three different interfaces • kind of synchronous behavior

18. 18 Next • Flash Controller • control oriented • three different interfaces • kind of synchronous behavior • Rise level of description (abstraction) • Two options : • SystemC-TLM • Multi-clock Esterel • Models control part in Esterel • See what could be TLM programming in Esterel

19. 19 SystemC vs Esterel • Clock driven + logical time • Input / Interface • Await() • Parallelism • Can describe different level of abstraction (maybe …) • Esterel multi-clock ? • Synthesis based approach • Static cycle must be avoided • Event driven + physical time • Input / Sensitivity list • Wait() • Parallelism emulation • Can describe different level of abstraction • PV to RTL • Simulation based approach • Activity stabilization (delta cycle)

20. 20 Q&A | Q&!A Thanks.

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24. 24 Convert sc_thread into sc_method + clock method1 << event << ready_to_restart do body1 emit event_start_count end do clock (min_time_resolution) method2 << event_start_count&clock do when event_start_count count time clock period emit event_time_elapsed end do method3 << event_time_elapsed do body2 emit event_time_elapsed end do thread << event loop wait(event) body1 wait(time) body2 end loop

25. 25 SystemC module representation Here state are methods that potentially emit signal when terminating and then activate other methods

26. 26 I/O esterel language FSM Bliff c/c++ esterel SystemC ? VHDL Verilog

27. 27 Esterel method representation Each method can be translate by a state running in parallel with the others and waiting on it sensitivity list to emit signal Loop await event1 emit refresh End loop Loop await event2 emit refresh End loop Loop await refresh if cond then emit event3 End loop