Applications of Boolean Satisfiability in Logic Synthesis and Verification

1. Applications of Boolean Satisfiability in Logic Synthesis and Verification Alan Mishchenko UC Berkeley

2. Outline • Introduction • Applications • Complete don’t-care computation • SAT sweeping • Computing initial state after retiming • Conclusion

3. Outline • Introduction • Applications • Complete don’t-care computation • SAT sweeping • Computing initial state after retiming • Conclusion

4. z1 z2 z3 x3 x1 x2 x4 x5 Terminology • Boolean network (netlist, circuit) • Primary inputs/outputs • Internal nodes • Fanins/fanouts of a node • Transitive fanin/fanout cone • Local functions of the nodes • Global functions of the nodes • Functionality of the network

5. Types of Don’t-Cares • Observation: Local function of a node can be changed as long as global functions of the network remain the same • This phenomenon gives rise to the notion of internal don’t-cares • Satisfiability don’t-cares (SDCs) • Local combinations, which never arise at the node • Observability don’t-cares (ODCs) • Global combinations, which make the output of the node not observable at the primary outputs • External don’t-cares (EXDCs) • Given by the designer • Derived using unreachable state information, etc • Complete don’t-cares (CDCs) • The largest don’t-care that can be associated with the node

6. F y x F b a a b c Examples of Don’t-Cares (x = 0, y = 1) is a satisfiability don’t-care for node F (a = 1, b = 1) is an observability don’t-care for node F The SDC is in the local space. The ODC is in the global space.

7. … n n Y Y X X Miter for Don’t-Care Computation

8. ODC and CDC Computation • Definition.The observability don’t-care of node n, ODC(X), is a Boolean function in the primary input space X taking value 1when the output of node n is not observed at the primary outputs. • Definition. The complete don’t-care of node n, CDC(Y),is aBoolean function in the local space Ytaking value 1when the output of node n is not observed at the primary outputs. f’(X) f(X) n n Y Y X X

9. n n Y Y X X Implementation • Compute the care set • Simulation • Simulate the miter using random patterns • Collect local minterms, for which the output of miter is 1 • This is a subset of a care set • Satisfiability • Assert the output of miter to be 1, add the negation of the care set computed by simulation, and enumerate through the SAT assignments • Add these assignments to the care set computed by simulation • Complement the care set to get CDC

10. Pseudo-Code Input: Node n in network S. Output: Complete don’t-cares of node n. function ComputeCompleteDC( node n , network S) { network G = ConstructMiter( S, n ); function F1 = RandomSimulation( G ); cnf P= CircuitToCNF( G) FunctionToCNF(F1); function F2= EnumerateSatSolutions( P ); return F1 F2; }

11. Outline • Introduction • Applications • Complete don’t-care computation • SAT sweeping • Computing initial state after retiming • Conclusion

12. … N2 N1 X X Terminology M • CEC • combinational equivalence checking • Miter • two circuits to be compared are combined by matching their primary inputs and comparing their primary outputs • Mitering • trying to prove output M = 0 using a SAT solver • SAT sweeping • trying to prove intermediate equivalences in topological order using a SAT solver M M SAT SAT-2 A B SAT-1 C D Mitering Fraiging

13. Primary outputs 1 ? D C 1 ? B A Primary inputs SAT Sweeping Algorithm • Works on an AIG • Collects equivalence candidates using simulation (e.g. {A,B}) • For each pair of candidate equivalent nodes in the topological order • Generates CNF from logic cones of A and B • Uses incremental interface of a SAT solver to prove/disprove candidates • Solves a sequence of SAT problems using the same solver • When two AIG nodes are proved equivalent, they are merged and the fanouts are rehashed • When two AIG nodes are proved different, the counter example is used to refine candidate classes • Stops when all candidates are considered

14. CNF-Based vs. Circuit-Based SAT • Traditionally, circuit problems are solved by circuit-based solvers • Circuit represents “high-level information” • Fast constraint propagation, better decisions • However, CNF-based solver made substantial progress • Constraint propagation became faster • Efficient circuit-to-CNF conversion make CNF-solving faster • Improved conflict analysis (clause minimization, etc) • What is lacking, is the “high-level information” available in circuits • Hybrid solvers are also available (Ganai, DAC ‘02; Jin, CAV ’04) • They are more complicated and may take longer to catch up with the latest improvements in CNF-based solving

15. Using Circuit Info in CNF-Based SAT • Using circuit-based information is often crucial for solving hard SAT instances originating from circuits • Two approaches to address this problem • Use circuit-based solver in CEC (A. Kuehlmann, TCAD’02) • Communicate circuit-based information to CNF-based solver (J. P. Marques-Silva et al, IEEE D&T,‘03) • Simulating J-frontier in a CNF-based solver

16. Biasing CNF-Based SAT Solver to Work for Circuits • Drawbacks of previous approaches • Circuit-based solvers do not use improvements in CNF-based solving • J-frontier may be costly to support in a CNF-based solver • We propose to modify variable activities in a CNF-based solver • After each restart, increase activities of some variables • Increase variable more if it is closer to the top of the miter M +3Δ +2Δ +Δ

17. Improved Integrated CEC • SAT sweeping is an important component of combinational equivalence checking (CEC) status IntegratedCEC( Miter, VariousResourceLimits ) { status = undecided; for ( Iter = 1; Iter <= IterLimit; Iter++ ) { // try mitering status = DoMitering( Miter, MiteringLimit + Iter * MiteringIncrease ); if ( status != undecided ) break; // try rewriting status = DoRewriting( Miter, RewritingLimit + Iter * RewritingIncrease ); if ( status != undecided ) break; // try fraiging status = DoSATSweeping( Miter, FraigingLimit + Iter * FraigingIncrease ); if ( status != undecided ) break; } if ( status != undecided ) status = DoMitering( Miter, FinalMiteringLimit ); if ( status == satisfiable ) Miter->CounterExample = GenerateCounterExample( Miter ); return status; }

18. Outline • Introduction • Applications • Complete don’t-care computation • SAT sweeping • Computing initial state after retiming • Conclusion

19. Motivation • Retiming can reduce the clock period of the circuit Critical path has delay 4 All paths have delay 2

20. Overview of Retiming • Goals of retiming • Minimum number of registers (min-area) • Min-area under delay constraints (min-delay) • Min-delay retiming with a valid initial state • Traditional formulation (Leiserson/Saxe, 1991) • Consider the network as a retiming graph • Generate constraints on the number of registers on each edge • Solve LP problem • Improved formulations • Improved constraint generation (Shenoy/Rudell, 1994) • Using retiming-skew equivalence (Sapatnekar et al, 1996/1998) • Using maximum-flow / minimum-cut (Hurst, 2008)

21. 0 1 0 ?   a+b a+b a+b a+b 0 ? 0 0 The Initial State Problem • In some cases, the initial state cannot be computed after backward retiming

22. Reset 1 Reset a+b a+b 0 1 Reset 1 a+b 0 0 0 1 A Solution to Initial State Problem • Additional hardware: multiplexers and a reset signal • Reset is 1 at the first clock, and 0 afterwards Detach initial values from latches Propagate constants in MUXes

23. Another Solution • Formulate a SAT problem that has solution if and only if there exists a valid initial state after backward retiming Register positions before retiming z3 z2 z1 Algorithm: • Covert circuit into CNF • Assign the given initial state to zi • Solve SAT problem • If solution exists, get initial state at xi • If solution does not exist, block some register moves and try again Register positions after backward retiming x3 x1 x2 x4 x5

24. What Register Moves to Disable? • Disable a minimum number of register moves, which causes the SAT problem to be UNSAT • To find these move, use the UNSAT core of the SAT problem • UNSAT core of a problem is a subset of CNF clauses which alone guarantee that the problem is UNSAT • Computing UNSAT core can be done using the resolution proof, which can be produced by the SAT solver

25. Resolvent A resolvent is a clause implied by two clauses in a CNF (a + C1)  (~a + C2) = (C1 + C2) 1. A SAT instance C 1. (~p + a)2. (~p + b) 3. (p + ~a + ~b) 4. (~q + a) 5. (~q + b) 6. (q + ~a + ~b) 7. (p + q + ~z) 8. (p + ~q + z) 9. (~p + q + z) 10. (~p + ~q + ~z) 11. (z) 2. Resolvent of clauses 3 and 4 (w.r.t.a)is the clause(p + ~b + ~q) 3. Adding the resolvent to the original set does not alter satisfiability: 1. (~p + a)2. (~p + b) 3. (p + ~a + ~b) 4. (~q + a) 5. (~q + b) 6. (q + ~a + ~b) 7. (p + q + ~z) 8. (p + ~q + z) 9. (~p + q + z) 10. (~p + ~q + ~z) 11. (z) 12. (p + ~b + ~q) C’ It can be checked that C’ is satisfiable if and only if C is.

26. Resolution Proof A resolution proof is a sequence of resolvents generated until the empty clause is derived. 1. Original set of clauses C 1. (~p + a)2. (~p + b) 3. (p + ~a + ~b) 4. (~q + a) 5. (~q + b) 6. (q + ~a + ~b) 7. (p + q + ~z) 8. (p + ~q + z) 9. (~p + q + z) 10. (~p + ~q + ~z) 11. (z) 2. Sequence of resolvents 12. (p + ~b + ~q) (from 3 and 4) 13. (p + ~q) (from 5 and 12) 14. (~p + q + ~a) (from 2 and 6) 15. (~p + q) (from 1 and 14) 16. (~p + ~q) (from 10 and 11) 17. (p + q) (from 7 and 11) 18. (~q) (from 13 and 16) 19. (q) (from 15 and 17) 20. () (from 18 and 19) If the empty clause i.e. () is derived by resolution then the original set of clauses is UNSAT Thus the sequence of resolution steps 12-20 forms a proof of unsatisfiability of C if () is derived at the end.

27. Using UNSAT Core • The proof can be traced back from the empty clause • Leads to a subset of original clauses, which participate in producing the empty clause • In the case of retiming, this subset is small • Typically, it is less than 1% of all clauses • The clauses indicate what nodes should not be retimed • In some case, the UNSAT-core can be iterated several times to prevent retiming of several groups of nodes • In the end, when the problem is SAT, the initial state after backward retiming is available

28. Conclusion • Discussed several applications of Boolean satisfiability in EDA applications • Complete don’t-care computation • Computing initial state after retiming • SAT sweeping