Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design

Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design Course and contest Results of Phase 1 Jacob Maxa, Hagen Fischer

FIR scheme • Adder: Ripple carry • Multiplier: unsigned carry skip multiplier • two's complement + sign extension • Optimizations X_in Reg0 Reg6 Reg7 Coeff 7 Coeff 0 Coeff 1 Coeff 8 0 ADD ADD ADD ADD Y_out Reg8

b3 a3 c3 b2 a2 c2 b1 a1 c1 b0 a0 Ripple Carry Adder FA FA FA HA Choose: • simple to implement (regular pattern) • only for prototyping • generate for 9* 40bit Adder • new component adder_comp • made of half-adder and full-adder components • variable bit-width for dynamic using Result: • works, no problems Optimization: • delete adder in first stage • no carry_out used cout S3 S2 S1 S0

b0a0 b1a1 b0a2 b1a0 b0a1 b1a2 b0a3 Carry Save Array Multiplier HA HA CSA HA b1a3 C S C S Choose: • simple for prototyping • faster than field array (critical path) • generate for 16bit *24bit (regular pattern) • new component mult_comp • made of existing adder components • variable bit-width Result: • complex debugging • problems with negative numbers Optimization: • need sign-extension • can be replaced with faster carry tree adder C S b2a2 b2a1 b2a0 FA FA FA b2a3 C S C S C S b3a2 b3a1 b3a0 FA FA FA b3a3 C S C S C S RCA HA FA FA a0 b0 p7 p6 p5 p4 p3 p2 p1 p0 a0 b0 =

Sign extension a3 a2 a1 a0 Choose: • generate for 16, 24 and 40bit • new component sign_extension • use of two's complement • made of half-adder and full-adder components • variable bit-width Result: • problems with “0 * negative = -0 ” Optimization: • Special logic for “+0” Sign ext. b3 b2 b1 b0 Multiplier Sign Sign ext. XOR

Results

Further steps • Implement optimized adder • Replace multiplier with signed multiplier • Use Wallace structure • Reduce bitsize of input signal an coefficients • Add pipelining to the stages • Some secret stuff

Thanks for your attention

Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design