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Computer Engineering 1502 Advanced Digital Design

Computer Engineering 1502 Advanced Digital Design. Professor Donald Chiarulli Computer Science Dept. don@cs.pitt.edu. Course Assistants and Resources. Sam Dickerson –TA Office – 271-I Benedum Hall sdickerson@ee.pitt.edu Joe Jesak -TA Office – 5426 Sennott Square ajnoyola@cs.pitt.edu.

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Computer Engineering 1502 Advanced Digital Design

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  1. Computer Engineering 1502Advanced Digital Design Professor Donald ChiarulliComputer Science Dept. don@cs.pitt.edu

  2. Course Assistants and Resources Sam Dickerson –TA Office – 271-I Benedum Hall sdickerson@ee.pitt.edu Joe Jesak -TA Office – 5426 Sennott Square ajnoyola@cs.pitt.edu

  3. Goals of this course • Learn tools and techniques of modern digital design for large scale digital systems • Complement your Computer Architecture Course (CoE 1541) with actual design experience for the processor covered in that course. • PREREQUISITE – CoE 0501 • CO-REQUISITE – CoE 1541 Pre/Co requisites are non-negotiable

  4. Things to do today After the presentation • Set up your account, make sure the tools work properly • Proceed with the tools tutorial, make sure that you do the library setup part. • Work on unit 1a up to (but not including “adding subblocks to block diagram”).

  5. What’s expected of you • Most of the work in this class is divided into a series of design units that will be combined into projects, two of which are processor designs • A design unit will begin with a lecture (approx 1 hour) at the beginning of class • You will have one or two weeks to complete the design unit depending on the complexity • Units will be checked individually by myself or the TA -- demonstrations are required to receive credit for a unit • Units not checked on the due date will be considered late with credit deducted • Units more than one week late will receive no credit (but you will still have to do them)

  6. Project 1: Design Tools and Methods • 2 person design groups • Design Units • Tools Tutorial - ALU design and Simulation • Testbench and assertion based test structure • ALU Synthesis and FPGA implementation

  7. Project 2 Multicycle CPU with State Machine Control • 2 person design group • Design Units • Multicycle CPU with state machine control (MIPS ISA) • Exception processing • Memory bus interface • Synthesis of multicycle CPU and hardware testing on FPGA board using logic analyzer

  8. Project 3Single issue pipeline CPU and primary cache • 4 person design group • Designated roles for each design group members (Designers,testers, project leader) • Simultaneous, parallel efforts on each design unit • Design units • 5-stage, single issue, pipelined processor (MIPS ISA) • Direct mapped primary cache • Individual test benches for CPU and cache • Synthesis and FPGA implementation of CPU/cache • Final project report

  9. Final Exam This is a design class, the final exam will test how effectively you have learned to tools and techniques of digital design You will be given the specification for a small device that you should be familiar with either from experiences in this or other classes You will be given two hours to implement this device using the software tools you have used in the course Grading will be based on completeness, functionality and quality of the design that you produce Since this is “almost” the only individual grade you will receive in this class, it will weigh heavily in the computation of your course grade

  10. Grading • All members of design group receive the same grade for the project • Project 1 - 10% (individual) • Project 2 - 30% (2 person group) • Project 3 - 30% (4 person group) • Final Exam - 30% (individual) • One of the main purposes of the final exam is to determine your level of participation in your group designs.

  11. Software Tools HDL Designer Suite - Mentor Graphics Inc FGPA Advantage - Design Entry Tool ModelSim - Simulator Xilinx - Design Synthesis FPGA place and Route tools

  12. Design Flow DesignEntry Verification VHDL FPGA Advantage ModelSim Xilinx LogicSynthesis Place and Route FPGA Hardware LogicAnalyzer

  13. Hardware platform:Field Programmable Gate Arrays “Wildfire” reconfigurable processing card • Xilinx Virtex-II Pro VP100 FPGA • 99K+ logic cells • 16MB x 64bit Ram • 64 bit channel logic analyzer interface • PCI bus host interface logic

  14. FPGA Structure

  15. Control Unit Integer ALU 32 x 32bit Register file Data Cache Inst. Cache Memory Interface Target CPU ArchitectureMIPS R2000* organization** • 3 address architecture • load/store machine • 32 x 32bit register file • three instruction formats • full version of the processor used in H+P text. • Intruction set reference on class web page * modified version for this class. ** Floating Point registers and ALU not shown

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