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Understanding Tasks and Timing Constraints in SystemVerilog for Digital Design

This module covers essential concepts of tasks and timing verification in SystemVerilog, specifically within the context of digital circuit design. It explores the creation and invocation of tasks, emphasizes the importance of clock-related timing constraints such as setup and hold conditions, and discusses the role of functions in aligning input data. Additional topics include static and dynamic timing analysis, signal period, pulse width, and the implications of clock skew. By grasping these concepts, designers can ensure reliable circuit behavior and performance.

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Understanding Tasks and Timing Constraints in SystemVerilog for Digital Design

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  1. Behavior Description 3 Lecture 12 ELEN 468

  2. Tasks (subroutines) module bit_counter (data, count); input [7:0] data; output [3:0] count; reg [3:0] count; always @(data) t(data, count); task t; input [7:0] a; output [3:0] c; reg [3:0] c; reg [7:0] tmp; begin c = 0; tmp = a; while (tmp) begin c = c + tmp[0]; tmp = tmp >> 1; end end endtask endmodule ELEN 468

  3. Task Rules • A task may be declared only within a module • A task may be called only from a procedural statement • A task may be called from the same module or from a different module by hierarchical de-referencing • A task can call itself • Variables may be defined locally within a task ELEN 468

  4. Functions module word_aligner (w_in, w_out); input [7:0] w_in; output [7:0] w_out; assign w_out = align (w_in); function [7:0] align; input [7:0] word; begin align = word; if (align != 0) while (align[7] == 0) align = align << 1; end endfunction endmodule ELEN 468

  5. Timing Verification • Static timing analysis • Consider structure topology of circuit, enumerate signal propagation paths and determine if timing constraints are met • Dynamic timing analysis • Simulate circuit timing using input vectors • Timing check tasks • $setup, $hold, $period, $width, $skew, $recovery, $nochange • Can be invoked within a behavior or testbench or in a specify block ELEN 468

  6. Setup Constraint • $setup(data, posedge clock, 5); • It specifies an interval before the active edge of clock. • Data must arrive before the interval. 5 5 clock data ELEN 468

  7. Hold Violation • $hold(data, posedge clock, 2); • It specifies an interval after the active edge of clock. • Data must be stable in the interval. 2 2 clock data ELEN 468

  8. SetupHold • $setuphold(data, posedge clock, 5, 2); 2 2 5 5 clock data ELEN 468

  9. Signal Period • $period(posedge clock, t_limit); • Signal period must be sufficiently long. clock cycle time clock t_limit ELEN 468

  10. Pulse Width • $width(posedge clock, t_mpw); • The width of the clock pulse must not be too small. clock pulse width clock t_mpw ELEN 468

  11. Clock Skew • $skew(negedge clk1, negedge clk2, t_skew); • Signal skew is the arriving time difference of two signals. • Clock skew should be limited. clk1 skew clk2 ELEN 468

  12. Recovery Time • $recovery(negedge bus_control, bus_driver, t_rec); • Time to go from Z to 0 or 1. Bus_control Bus_driver Z t_rec ELEN 468

  13. No Signal Change • $nochange(posedge clk, data, -5, 2); • Equivalent to • $setuphold(data, posedge clk, 5, 2); ELEN 468

  14. Finite State Machines • Explicit FSM • States are defined explicitly • FSM_style1 (page 240) • Minimum behavioral description • FSM_style2 (page 240 • Use behavioral to define next state, easier to use • FSM_style3 (page 241) • Output synchronized with clock ELEN 468

  15. Example 7.58 (page 242) ELEN 468

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