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Interrupts and Exception Handling in MIPS Architecture

This document covers the mechanisms of interrupts and exceptions in MIPS architecture. It explains events that alter the standard instruction flow, including arithmetic overflow, invalid instruction errors, and system calls. Essential hardware components like the EPC, Cause, and Status registers are discussed, highlighting their roles in managing exceptions and interrupts. The handling process includes saving the program counter, determining the exception type, and executing the appropriate handler. Key instructions for implementing these functionalities are also outlined.

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Interrupts and Exception Handling in MIPS Architecture

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  1. COE 1502Interrupt and Exception Handling

  2. Interrupts and Exceptions • Events other than branches that change the normal flow of instruction execution • Exceptions • Unexpected event from inside the processor • Arithmetic overflow, divide-by-zero • Invalid instruction (bus error) • L/S address error (misalignment, attempted access to protected memory) • Reserved/privileged instruction • Syscall (invoking the OS from user program) • Breakpoint • Interrupts • Unexpected event from outside the processor • I/O device request • Timer • Additional information • H&P text

  3. Exceptions • We will implement: • Arithmetic overflow • add, addi, sub • Use overflow output from ALU • Write-back result? • System call • OS services • I/O, process control, process synchonization • Invalid instruction • Invalid opcode/function code • Lowest priority, unconditional transitions

  4. Interrupts • Must implement way for external devices to get the processor’s attention • Assume 1 external interrupt • Signals processor through IRQ input • Processor signals completion through IACK output • Want to complete current instruction before servicing interrupt

  5. Interrupts and Exceptions • What to do? • Execute code in response to event (handler) • Save PC (EPC reg,) • Record cause (Cause reg.) • Disable e/i (shift Status reg.) • Set new PC (4) • Return from handler • Restore PC • Enable e/i (shift Status reg.) • Determining type of exception • Use vectored exceptions • Infer type from address • Use polled exceptions • Use Cause register • This is what MIPS does

  6. Required Hardware • Hardwired handler address • EPC register • Address of instruction that caused exception + 4 (PC) • Cause register • 32-bit register that holds cause of exception • Status register (shiftable) • Use for disabling interrupts and exceptions • Additional control and datapaths

  7. Cause Register • Use last 2 bits…

  8. Status Register • Use last 4 bits…

  9. Control • When an exception or interrupt occurs, must have a state where… • EPC <= PC • Cause <= (cause) • Status <= Status << 4 • PC <= (handler address) • Return… • PC <= EPC • Status >> 4 • How to add states?

  10. Required Hardware

  11. Required Instructions • EPC, Status, and Cause registers • Instruction set treats these registers as being on coprocessor 0 • Status (12), Cause (13), and EPC (14) • To use these registers, we’ll implement two instructions: • mfc0 rt, rd • mtc0 rd, rt • Datapath analysis for these instructions?

  12. Required Instructions • Also, we need a syscall instruction to implement system calls • Syscall call value in $v0 • Return from exception (rfe instruction)

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