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The Wires

EE5900 Advanced Algorithms for Robust VLSI CAD. Dr. Shiyan Hu Office: EERC 731. The Wires. Adapted and modified from Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic. Modern Interconnect. Modern Interconnect - II.

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The Wires

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  1. EE5900 Advanced Algorithms for Robust VLSI CAD Dr. Shiyan Hu Office: EERC 731 The Wires Adapted and modified from Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic.

  2. Modern Interconnect

  3. Modern Interconnect - II

  4. Interconnect Delay Dominates 300 250 Interconnect delay 200 150 Delay (psec) 100 Transistor/Gate delay 50 0 0.25 0.8 0.5 0.35 0.25 0.18 0.15 Technology generation (m) Source: Gordon Moore, Chairman Emeritus, Intel Corp.

  5. Wire Model

  6. Capacitor • A capacitor is a device that can store an electric charge by applying a voltage • The capacitance is measured by the ratio of the charge stored to the applied voltage • Capacitance is measured in Farads

  7. 3D Parasitic Capacitance • Given a set of conductors, compute the capacitance between all pairs of conductors. 1V + - - + + + - C=Q/V - + - - -

  8. Simplified Model • Area capacitance (Parallel plate): area overlap between adjacent layers/substrate • Fringing/coupling capacitance: • between side-walls on the same layer • between side-wall and adjacent layers/substrate m3 m2 m2 m2 m1

  9. The Parallel Plate Model (Area Capacitance) Capacitance is proportional to the overlap between the conductors and inversely proportional to their separation

  10. Wire Capacitance • More difficult due to multiple layers, different dielectric =8.0 m3 multiple dielectric =4.0 m2 m2 m2 =3.9 =4.1 m1

  11. Simple Estimation Methods - I • C = Ca*(overlap area) +Cc*(length of parallel run) +Cf*(perimeter) • Coefficients Ca, Cc and Cf are given by the fab • Cadence Dracula • Fast but inaccurate

  12. Simple Estimation Methods - II • Consider interaction between layer i and layers i+1, i+2, i–1 and i–2 • Consider distance between conductors on the same layer • Cadence Silicon Ensemble • Accuracy 50%

  13. Library Based Methods • Build a library of tens of thousands of patterns and compute capacitance for each pattern • Partition layout into blocks, and match with the library • Accuracy 20%

  14. Accurate Methods In Industry • Finite difference/finite element method • Most accurate, slowest • Raphael • Boundary element method • FastCap, Hicap

  15. Fringing versus Parallel Plate Fringing/Coupling capacitance dominates.

  16. Wire Resistance • Basic formula R=(/h)(l/w) •  : resistivity • h: thickness, fixed for a given technology and layer number • l: conductor length • w: conductor width l h w

  17. Typical Rs (Ohm/sq)

  18. Contact and Via • Contact: • link metal with diffusion (active) • Link metal with gate poly • Via: • Link wire with wire • Overlapping two layers (diffusion, gate poly or metal) and providing a contact hole filled with metal • Substrate Contact and Well Contact: • Link substrate or well to supply voltage

  19. Interconnect Delay

  20. Analysis of Simple RC Circuit i(t) R v(t) vT(t) C ± state variable Input waveform

  21. v0u(t) v0 v0(1-e-t/RC)u(t) Analysis of Simple RC Circuit Step-input response: match initial state: output response for step-input:

  22. 0.69RC • v(t) = v0(1 - e-t/RC) -- waveform under step input v0u(t) • v(t)=0.5v0  t = 0.69RC • i.e., delay = 0.69RC (50% delay) v(t)=0.1v0 t = 0.1RC v(t)=0.9v0 t = 2.3RC • i.e., rise time = 2.2RC (if defined as time from 10% to 90% of Vdd) • For simplicity, industry uses TD = RC (= Elmore delay) • We use both RC and 0.69RC in this course.

  23. Elmore Delay • 50%-50% point delay • Delay=RC • (Precisely, 0.69RC) Delay

  24. Elmore Delay - III What is the delay of a wire?

  25. Elmore Delay – IV Assume: Wire modeled by N equal-length segments For large values of N: Precisely, should be 0.69RC/2

  26. Elmore Delay - V n2 n1 n1 n2 C/2 C/2 R R=unit wire resistance*length C=unit wire capacitance*length

  27. RC Tree Delay 4 4 2 2 7 2 7 24+4*2=32 3.5 1 2 1 3.5 Unit wire cap=1, unit wire res=1 2*(1+3.5+3.5+2+2)=24 24+7*3.5=48.5 Precisely, 0.69*48.5 RC Tree Delay=max{32,48.5}=48.5

  28. Summary • Wire capacitance • Fringing/coupling capacitance dominates area capacitance • Wire resistance • RC Elmore delay model for wire • For single wire, 0.69RC/2 • RC tree

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