1 / 23

ELEC 2200-002 Digital Logic Circuits Fall 2015 Delay and Power

ELEC 2200-002 Digital Logic Circuits Fall 2015 Delay and Power. Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu. Power and Delay of a Transition.

issac
Télécharger la présentation

ELEC 2200-002 Digital Logic Circuits Fall 2015 Delay and Power

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. ELEC 2200-002Digital Logic CircuitsFall 2015Delay and Power Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu ELEC2200-002 Lecture 8

  2. Power and Delay of a Transition VDD Ron ic(t) vi (t) vo(t) CL R = large Ground CL = Total load capacitance for gate; includes transistor capacitances of driving gate + routing capacitance + transistor capacitances of driven gates; obtained by layout analysis. ELEC2200-002 Lecture 8

  3. Charging of a Capacitor R = Ron t = 0 v(t) i(t) C = CL VDD Charge on capacitor, q(t) = C v(t) Current, i(t) = dq(t)/dt = C dv(t)/dt ELEC2200-002 Lecture 8

  4. i(t) = C dv(t)/dt = [VDD – v(t)] /R dv(t) dt ∫───── = ∫ ──── VDD – v(t) RC – t ln [VDD – v(t)] = ── + A RC Initial condition, t = 0, v(t) = 0 → A = ln VDD – t v(t) = VDD[1 – exp(───)] = 0.5VDD RC t = 0.69 RC ELEC2200-002 Lecture 8

  5. Delay: Definitions • Rise time is the time a signal takes to rise from 10% to 90% of its peak value. • Fall time is the time a signal takes to drop from 90% to 10% of its peak value. • Delay of a gate or circuit is the time interval between the input crossing 50% of peak value and the output crossing 50% of peak value. VDD GND 90% VDD A Fall time 10% VDD Time B Gate delay A NOT gate 1→0 VDD GND 0→1 90% VDD B Rise time 10% VDD ELEC2200-002 Lecture 8 Time

  6. Inverter: Idealized Input VDD GND INPUT Gate delay VDD 0.5VDD GND OUTPUT time t= 0 0.69CR ELEC2200-002 Lecture 8

  7. Timing of a Digital Circuit • Most digital circuits are clocked synchronous finite state machines (FSM). FF FF Primary Inputs Primary Outputs Combinational circuit (Gates interconnected without feedback) FF FF Clock FF FF ELEC2200-002 Lecture 8

  8. Large Circuit Timing Analysis • Determine gate delays: • From layout analysis, or use approximate delays: • Gate delay increases in proportion to number of fanouts (increased capacitance) • Delay decreases in proportion to increase in gate size (reduced transistor channel resistance) • Purpose of analysis is to verify timing behavior – determine maximum speed of operation. • Methods of analysis: • Circuit simulation – most accurate, expensive (Spice program) • Static timing analysis (STA) – most efficient, approximate ELEC2200-002 Lecture 8

  9. Static Timing Analysis (STA) • Combinational logic for critical path delays. • Circuit represented as an acyclic directed graph (DAG). • Gates characterized by delays; gate function ignored. • No inputs are used – worst-case analysis – static analysis (simulation would be dynamic). ELEC2200-002 Lecture 8

  10. Combinational Circuit of an FSM A 1 H 1 Gate delay B 1 E 4 G 1 Fanout = 4 C 2 J 1 F 2 D 1 Input to Output delay must not exceed clock period ELEC2200-002 Lecture 8

  11. Static Timing Analysis (STA) Step 1 Levelize circuit. Initialize arrival times at primary inputs to 0. 0 0 A 1 H 1 0 0 B 1 E 4 G 1 0 0 C 2 J 1 F 2 0 0 D 1 Level of a gate is one greater than the maximum of fanin gate levels Level 0 1 2 3 4 5 ELEC2200-002 Lecture 8

  12. Static Timing Analysis (STA) Step 2 Determine output arrival times of gates in level order. 0 0 1 A 1 10 H 1 0 0 1 B 1 6 E 4 9 G 1 0 0 C 2 2 9 J 1 F 2 0 0 8 1 D 1 Arrival time at a gate output = maximum of input arrivals + gate delay Level 0 1 2 3 4 5 ELEC2200-002 Lecture 8

  13. Static Timing Analysis (STA) Step 3 Trace critical paths from the output with longest arrival time. 0 0 1 A 1 10 H 1 0 0 1 B 1 6 E 4 9 G 1 0 0 C 2 2 9 J 1 F 2 0 0 8 1 D 1 Critical path: C, E, F, G, H; delay = 10 Level 0 1 2 3 4 5 ELEC2200-002 Lecture 8

  14. Power in CMOS Logic (Inverter) VDD No current flows from power supply! Where is power consumed? GND F. M. Wanlass and C. T. Sah, “Nanowatt Logic using Field-Effect Metal-Oxide-Semiconductor Triodes,” IEEE International Solid-State Circuits Conference Digest, vol. IV, February 1963, pp. 32-33. ELEC2200-002 Lecture 8

  15. Three Components of Power • Dynamic, when output changes • Signal transitions (major component) • Logic activity • Glitches • Short-circuit (small, often neglected) • Static, when signal is in steady state • Leakage (small) Ptotal = Pdyn + Pstat = Ptran +Psc+Pstat ELEC2200-002 Lecture 8

  16. Charging of Output Capacitor • From Slide 4: – t v(t) = V [1 – exp(── )] RC dv(t) V – t i(t) = C ─── = ── exp(── ) dt R RC ELEC2200-002 Lecture 8

  17. Total Energy Per Charging Transition from Power Supply ∞∞ V 2 – t Etrans = ∫ V i(t) dt = ∫ ── exp(── ) dt 00 R RC = CV 2 ELEC2200-002 Lecture 8

  18. Energy Dissipated Per Transition in Transistor Channel Resistance ∞ V 2∞ -2t R ∫ i2(t) dt = R ── ∫ exp(── ) dt 0 R20 RC 1 = ─ CV 2 2 ELEC2200-002 Lecture 8

  19. Energy Stored in Charged Capacitor ∞ ∞ - t V - t ∫ v(t) i(t) dt = ∫ V [1-exp(── )]─ exp(── ) dt 00 RC R RC 1 = ─ CV 2 2 ELEC2200-002 Lecture 8

  20. Transition Power • Gate output rising transition • Energy dissipated in pMOS transistor = ½CV 2 • Energy stored in capacitor = ½CV 2 • Gate output falling transition • Energy dissipated in nMOS transistor = ½ CV 2 • Energy dissipated per transition = ½ CV 2 • Power dissipation: Ptrans = Etransα fck = ½ α fck CV 2 α = activity factor = prob.(gate has transition) fck = clock frequency ELEC2200-002 Lecture 8

  21. Power Density of a Chip • Assume dynamic power is major component. • Power density = ½ αfck CV 2 × gate density • C = average gate capacitance • Gate density = number of gates per unit area • Example: α = 0.5, fck= 1GHz, C = 1pF, V = 1 volt, gate density = 1 million gates/cm2 Power density = 250 watts/cm2 ELEC2200-002 Lecture 8

  22. CMOS Gate Power Output signal transition Dynamic current Short-circuit current Leakage current v(t) V R = Ron i(t) vi (t) v(t) i(t) Large resistance C isc(t) isc(t) Ground Leakage current time ELEC2200-002 Lecture 8

  23. References • Delay modeling, simulation and testing: • M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Springer, 2000. • Timing analysis and design: • G. De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994. • N. Maheshwari and S. S. Sapatnekar, Timing Analysis and Optimization of Sequential Circuits, Springer, 1999. • PrimeTime (A static timing analysis tool): • H. Bhatnagar, Advanced ASIC Chip Synthesis, Second Edition, Springer, 2002 • CMOS digital circuit power: • A. Chandrakasan and R. Brodersen, Low-Power Digital CMOS Design, Boston: Springer, 1995. ELEC2200-002 Lecture 8

More Related