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Lecture 13: Pipeline Control and Exceptions

This lecture covers pipeline control and exceptions in computer architecture, specifically focusing on ideal pipelining and different hazards in the pipeline. The lecture is delivered by Professor Mike Schulte.

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Lecture 13: Pipeline Control and Exceptions

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  1. Lecture 13: Pipeline Control and Exceptions Professor Mike Schulte Computer Architecture ECE 201

  2. Recap: Ideal Pipelining Assume instructions are completely independent! Maximum Speedup £ Number of stages Speedup £ Time for unpipelined operation Time for longest stage IF DCD EX MEM WB IF DCD EX MEM WB IF DCD EX MEM WB IF DCD EX MEM WB IF DCD EX MEM WB Example: 40ns data path, 5 stages, Longest stage is 10 ns, Speedup £ 4

  3. A M S B D Recap: Control Diagram IR <- Mem[PC]; PC < PC+4; A <- R[rs]; B<– R[rt] S <– A + B; S <– A or ZX; S <– A + SX; S <– A + SX; If Cond PC < PC+SX; M <– S M <– Mem[S] Mem[S] <- B M <– S R[rd] <– S; R[rt] <– S; R[rd] <– M; Equal Reg. File Reg File Exec PC IR Next PC Inst. Mem Mem Access Data Mem

  4. But recall use of “Data Stationary Control” • The Main Control generates the control signals during Reg/Dec • Control signals for Exec (ExtOp, ALUSrc, ...) are used 1 cycle later • Control signals for Mem (MemWr Branch) are used 2 cycles later • Control signals for Wr (MemtoReg MemWr) are used 3 cycles later Reg/Dec Exec Mem Wr ExtOp ExtOp ALUSrc ALUSrc ALUOp ALUOp Main Control RegDst RegDst Ex/Mem Register IF/ID Register Mem/Wr Register ID/Ex Register MemWr MemWr MemWr Branch Branch Branch MemtoReg MemtoReg MemtoReg MemtoReg RegWr RegWr RegWr RegWr

  5. A M S B D PC Datapath + Data Stationary Control IR v v v fun rw rw rw wb wb wb Inst. Mem Decode me me WB Ctrl rt Mem Ctrl rs ex op im rs rt Reg. File Reg File Exec Mem Access Data Mem Next PC

  6. Let’s Try it Out 10 lw r1, r2(35) 14 addI r2, r2, 3 20 sub r3, r4, r5 24 beq r6, r7, 100 30 ori r8, r9, 17 34 add r10, r11, r12 100 and r13, r14, 15 these addresses are octal

  7. n n n n A M S B = IF D Next PC 10 PC Start: Fetch 10 Inst. Mem Decode WB Ctrl Mem Ctrl IR im rs rt Reg. File Reg File Exec Mem Access Data Mem 10 lw r1, r2(35) 14 addI r2, r2, 3 20 sub r3, r4, r5 24 beq r6, r7, 100 30 ori r8, r9, 17 34 add r10, r11, r12 100 and r13, r14, 15

  8. n n n A M S B = ID D IF Next PC 14 PC Fetch 14, Decode 10 lw r1, r2(35) Inst. Mem Decode WB Ctrl Mem Ctrl IR im 2 rt Reg. File Reg File Exec Mem Access Data Mem 10 lw r1, r2(35) 14 addI r2, r2, 3 20 sub r3, r4, r5 24 beq r6, r7, 100 30 ori r8, r9, 17 34 add r10, r11, r12 100 and r13, r14, 15

  9. n n M S B = D ID IF Next PC 20 PC Fetch 20, Decode 14, Exec 10 addI r2, r2, 3 Inst. Mem Decode WB Ctrl lw r1 Mem Ctrl IR 35 2 rt Reg. File Reg File r2 Exec Mem Access Data Mem EX 10 lw r1, r2(35) 14 addI r2, r2, 3 20 sub r3, r4, r5 24 beq r6, r7, 100 30 ori r8, r9, 17 34 add r10, r11, r12 100 and r13, r14, 15

  10. n M B = D EX ID Next PC 24 IF PC Fetch 24, Decode 20, Exec 14, Mem 10 sub r3, r4, r5 addI r2, r2, 3 Inst. Mem Decode WB Ctrl lw r1 Mem Ctrl IR 3 4 5 Reg. File Reg File r2 r2+35 Exec Mem Access Data Mem M 10 lw r1, r2(35) 14 addI r2, r2, 3 20 sub r3, r4, r5 24 beq r6, r7, 100 30 ori r8, r9, 17 34 add r10, r11, r12 100 and r13, r14, 15

  11. r5 = WB D M EX Next PC ID 30 IF PC Fetch 30, Dcd 24, Ex 20, Mem 14, WB 10 beq r6, r7 100 Inst. Mem Decode WB Ctrl addI r2 sub r3 lw r1 Mem Ctrl IR 6 7 Reg. File Reg File r4 M[r2+35] r2+3 Exec Mem Access Data Mem 10 lw r1, r2(35) 14 addI r2, r2, 3 20 sub r3, r4, r5 24 beq r6, r7, 100 30 ori r8, r9, 17 34 add r10, r11, r12 100 and r13, r14, 15 Note Delayed Branch: always execute ori after beq

  12. r7 = D Next PC EX 100 ID PC IF Fetch 100, Dcd 30, Ex 24, Mem 20, WB 14 ori r8, r9 17 Inst. Mem Decode WB Ctrl addI r2 sub r3 Mem Ctrl beq IR 9 xx 100 r1=M[r2+35] Reg. File Reg File r6 r2+3 r4-r5 Exec Mem Access Data Mem 10 lw r1, r2(35) 14 addI r2, r2, 3 20 sub r3, r4, r5 24 beq r6, r7, 100 30 ori r8, r9, 17 34 add r10, r11, r12 100 and r13, r14, 15 WB M

  13. = D WB Next PC M ___ EX PC ID Fetch 104, Dcd 100, Ex 30, Mem 24, WB 20 ? Inst. Mem Decode WB Ctrl Mem Ctrl IR Reg. File Reg File Exec Mem Access Data Mem 10 lw r1, r2(35) 14 addI r2, r2, 3 20 sub r3, r4, r5 24 beq r6, r7, 100 30 ori r8, r9, 17 34 add r10, r11, r12 100 and r13, r14, 15 Fill it in yourself!

  14. = D Next PC WB ___ PC EX Fetch 110, Dcd 104, Ex 100, Mem 30, WB 24 ? ? Inst. Mem Decode WB Ctrl Mem Ctrl IR ? Reg. File Reg File ? Exec Mem Access Data Mem 10 lw r1, r2(35) 14 addI r2, r2, 3 20 sub r3, r4, r5 24 beq r6, r7, 100 30 ori r8, r9, 17 34 add r10, r11, r12 100 and r13, r14, 15 M Fill it in yourself!

  15. = D Next PC ___ WB PC Fetch 114, Dcd 110, Ex 104, Mem 100, WB 30 ? ? ? Inst. Mem Decode WB Ctrl Mem Ctrl IR ? Reg. File Reg File ? ? Exec Mem Access Data Mem 10 lw r1, r2(35) 14 addI r2, r2, 3 20 sub r3, r4, r5 24 beq r6, r7, 100 30 ori r8, r9, 17 34 add r10, r11, r12 100 and r13, r14, 15 Fill it in yourself! M

  16. Pipeline Hazards Again I-Fet ch DCD MemOpFetch OpFetch Exec Store IFetch DCD ° ° ° Structural Hazard I-Fet ch DCD OpFetch Jump Control Hazard IFetch DCD ° ° ° IF DCD EX Mem WB RAW (read after write) Data Hazard IF DCD EX Mem WB WAW Data Hazard (write after write) IF DCD EX Mem WB IF DCD OF Ex Mem IF DCD OF Ex RS WAR Data Hazard (write after read)

  17. RAW Data Hazard IF DCD EX Mem WB IF DCD EX Mem WB WAW Data Hazard IF DCD EX Mem WB IF DCD OF Ex Mem IF DCD OF Ex RS RAW Data Hazard Data Hazards • Avoid some “by design” • eliminate WAR by always fetching operands early (DCD) in pipe • eleminate WAW by doing all WBs in order (last stage, static) • Detect and resolve remaining ones • stall or forward (if possible)

  18. Hazard Detection • Suppose instruction i is about to be issued and a predecessor instruction j is in the instruction pipeline. • A RAW hazard exists on register r if r Î Rregs( i ) Ç Wregs( j ) • Keep a record of pending writes (for inst's in the pipe) and compare with operand regs of current instruction. • When instruction issues, reserve its result register. • When on operation completes, remove its write reservation. • A WAW hazard exists on register r if r Î Wregs( i ) Ç Wregs( j ) • A WAR hazard exists on register r if r Î Wregs( i ) Ç Rregs( j )

  19. Record of Pending Writes IAU • Current operand registers • Pending writes • hazard <= ((rs == rwex) & regWex) OR ((rs == rwmem) & regWme) OR ((rs == rwwb) & regWwb) OR ((rt == rwex) & regWex) OR ((rt == rwmem) & regWme) OR ((rt == rwwb) & regWwb) npc I mem Regs op rw rs rt PC im n op rw B A alu n op rw S D mem m n op rw Regs

  20. Resolve RAW by forwarding IAU • Detect nearest valid write op operand register and forward into op latches, bypassing remainder of the pipe • Increase muxes to add paths from pipeline registers • Data Forwarding = Data Bypassing npc I mem Regs op rw rs rt PC Forward mux im n op rw B A alu n op rw S D mem m n op rw Regs

  21. What about memory operations? ° If instructions are initiated in order and operations always occur in the same stage, there can be no hazards between memory operations! ° What does delaying WB on arithmetic operations cost? – cycles ? – hardware ? ° What about data dependence on loads? R1 <- R4 + R5 R2 <- Mem[ R2 + I ] R3 <- R2 + R1 => op Rd Ra Rb op Rd Ra Rb A B Rd R "Delayed Loads" T Rd to reg file

  22. Compiler Avoiding Load Stalls:

  23. What about Interrupts, Traps, Faults? • External Interrupts: • Allow pipeline to drain, • Load PC with interupt address • Faults (within instruction, restartable) • Force trap instruction into IF • disable writes till trap hits WB • must save multiple PCs or PC + state Refer to MIPS solution

  24. Exception Handling IAU npc detect bad instruction address I mem Regs lw $2,20($5) PC detect bad instruction im n op rw B A detect overflow alu S detect bad data address D mem m Allow exception to take effect Regs

  25. Exception Problem • Exceptions/Interrupts: 5 instructions executing in 5 stage pipeline • How to stop the pipeline? • Restart? • Who caused the interrupt? Stage Problem interrupts occurring IF Page fault on instruction fetch; misaligned memory access; memory-protection violation ID Undefined or illegal opcode EX Arithmetic exception MEM Page fault on data fetch; misaligned memory access; memory-protection violation; memory error • Load with data page fault, Add with instruction page fault? • Solution 1: interrupt vector/instruction

  26. Resolution: Freeze above & Bubble Below IAU npc I mem freeze Regs op rw rs rt PC bubble im n op rw B A alu n op rw S D mem m n op rw Regs

  27. Resource Usage TLB TLB I-cache RF WB ALUALU D-Cache MIPS R3000 Instruction Pipeline Decode Reg. Read Inst Fetch ALU / E.A Memory Write Reg TLB I-Cache RF Operation WB E.A. TLB D-Cache Write in phase 1, read in phase 2 => eliminates bypass from WB

  28. Time (clock cycles) IF ID/RF EX MEM WB add r1,r2,r3 Reg Reg ALU Im Dm I n s t r. O r d e r sub r4,r1,r3 Im Dm Reg Reg ALU Im Dm Reg Reg and r6,r1,r7 ALU Im Dm Reg Reg or r8,r1,r9 ALU Im Dm Reg Reg ALU xor r10,r1,r11 Recall: Data Hazard on r1 With MIPS R3000 pipeline, no need to forward from WB stage

  29. MIPS R3000 Multicycle Operations op Rd Ra Rb Ex: Multiply, Divide, Cache Miss Stall all stages above multicycle operation in the pipeline Drain (bubble) stages below it Use control word of local stage state to step through multicycle operation mul Rd Ra Rb A B Rd R Rd T to reg file

  30. Issues in Pipelined design Limitation IF D Ex M W ° Pipelining IF D Ex M W IF D Ex M W Issue rate, FU stalls, FU depth IF D Ex M W ° Super-pipeline - Issue one instruction per (fast) cycle IF D Ex M W - ALU takes multiple cycles IF D Ex M W Clock skew, FU stalls, FU depth IF D Ex M W IF D Ex M W ° Super-scalar Hazard resolution IF D Ex M W IF D Ex M W - Issue multiple scalar IF D Ex M W instructions per cycle IF D Ex M W ° VLIW (“EPIC”) - Each instruction specifies Packing IF D Ex M W multiple scalar operations - Compiler determines parallelism Ex M W Ex M W Ex M W ° Vector operations Applicability IF D Ex M W - Each instruction specifies Ex M W Ex M W series of identical operations Ex M W

  31. Partitioned Instruction Issue (simple Superscalar) independent int and FP issue to separate pipelines I-Cache Int Reg Inst Issue and Bypass FP Reg Operand / Result Busses Int Unit Load / Store Unit FP Add FP Mul D-Cache Single Issue Total Time = Int Time + FP Time Max Speedup: Total Time MAX(Int Time, FP Time)

  32. A B R D$ T Multiple Pipes/ Harder Superscalar • Issues: • Reg. File ports • Detecting Data • Dependences • Bypassing • RAW Hazard • WAR Hazard • Multiple load/store ops? • Branches IR0 IR1 Register File B A R D$ T

  33. Branch penalties in superscalar Example: resolved in op-fetch stage, single exposed delay (ala MIPS, Sparc) I-fetch Branch delay Squash 2 I-fetch Branch Squash 1 delay

  34. Summary • Pipelines pass control information down the pipe just as data moves down pipe • Forwarding/Stalls handled by local control • Exceptions stop the pipeline • MIPS I instruction set architecture made pipeline visible (delayed branch, delayed load) • More performance from deeper pipelines, parallelism

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