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last updated april 26 2007 n.
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Last updated: April 26, 2007 PowerPoint Presentation
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Last updated: April 26, 2007

Last updated: April 26, 2007

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Last updated: April 26, 2007

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  1. Moto Q GSM Last updated: April 26, 2007

  2. Block Diagram

  3. Board Layout

  4. RF Overview

  5. Antenna • NOTE • Accessory port only used for test purposes • Not designed to support RF cabled accessories Band Support

  6. RF6029 Features • EDGE Polar Modulator • Frac-N Digital GMSK Modulator • Integrated VCOs, Loop Filters, 4 RX SAW Filters, Matching, Bypass Caps • On-Chip Reference Oscillator Outputs (26MHz or 13MHz to Baseband) • Analog I/Q and Digital Baseband Interfaces • VLIF and DCR RX Modes • SAIC Capable • Two DACs: Power Amplifier Ramp and Frequency Control • 10mmx10mm Leadless Package

  7. RF6029 Neptune RF3178

  8. RF3178 Features • Integrated Antenna Switch • Capable of transmitting and receiving GSM/GPRS/EDGE signals in GSM850/900/1800/1900MHz bands • Includes two separate GaAs dies for PA line-ups • One single CMOS die for the controller to control output power and RF switch • Single PHEMT die for the RF switch

  9. RF3178 RF6029 RF6029

  10. Antenna Truth Table

  11. RF Interface • RX signals from antenna flow to RF6029 through RF switch inside RF3178. Signals are filtered, amplified, mixed, converted to IQ and digitized before sending to the Base Band IC. • The transmitter IQ is modulated directly into the TxVCO’s, buffered then sent to RF3178 for amplification. • Vramp used to control PA output power. Signal includes amplitude and timing of ramp up sequence, final power level, and ramping down of the TX burst. DAC values are programmed through SPI interface in the registers inside RF6029. • Vsense is used to monitor the current drain of the PA. • B1, B2 and B3 are used to control RF switch. The values of these signals are stored in register inside RF6029. • MS, MCLK, and MDI from Neptune to RF6029 are TX modulation sync, clock and TXQ/TXIB analog signals. • DRI, FSR and CLKR from RF6029 to Neptune are digital serial RX data interface frame sync or Q analog signal and digital serial RX data interface clock or IB analog signals. • OSCO from RF6029 to Neptune is a digital clock. It is used as system clock of the radio. Its frequency is dependent of OSCOM. • SPI from Neptune to RF6029 is used to program the RF6029. • TX_START, ENR, RX_ANT_EN are transmit start, digital serial RX data interface enable and receiver enable.

  12. Interface Block Diagram

  13. Baseband Overview

  14. PCAP Power Distribution • (SW1) AP_CORE 1.2V ± 5%  This voltage varies between 1.0V to 1.35 depending on the AP processor State and clock rate. Source for Bulverde core. • (SW2) VBUCK, 1.875V ± 4% Source for Neptune Memory , Display IO, & Bulverde Memory. • V1 = AP_IO_REG, 2.775V ± 3% Sources PCAP Internal logic, EMU VCCIO, Camera, Display DC/DC, Keypad, Bluetooth IO,  EL Driver IO, Neptune and Bulverde I/O. • V2 =  V_AUDIO , 2.775V ± 3% Sources PCAP Internal Audio logic, Neptune audio clock. • V3 =  VAP_SRAM , 1.275V ± 3%  starts at 1.275V and then lowers to 1.05V. Sources Bulverde VCC_SRAM • V4 =  VRF_TXRX , 2.775V ± 3% Sources  PRIME Chipset. • V5 =  VRF_VCO , 2.775V ± 3% Source for PRIME Chipset. • V6 =  VCAM_AN , 2.775V ± 3% Source for Camera Analog • V7 =  VRF_LNA , 2.775V ± 3% Sources  PRIME  Chipset. • V8 =  VAP_PLL , 1.275V ± 3% Source for Bulverde VCC_PLL. • V9 =  VBB_REF , 1.575V ± 3% Source for Neptune  and PCAP RTC. • VAUX1 =  VBT_RF ,  1.875 V ± 5% Source for Bluetooth RF Base band. • VAUX2 =  VAP_MMC ,  1.8 and  3V ± 5% Source for Mini SD external flash memory and SDIO application cards. • VSIM = SIM_VCC 3.0V +- 5% Supplies SIM card power.

  15. PCAP Clock • 32kHz clock used for power savings and RTC operations • Clock frequency generated from external 32.768 kHz crystal • PCAP also contains an internal RC oscillator that runs at 32.768 kHz nominal frequency • The RC oscillator will be used to run the debounce logic, PLL, and internal control logic. • The 32 kHz oscillator is powered at all times with valid voltage source is present at Battery, USB power, or coin cell battery for Real Time clock maintenance.

  16. PCAP Clock Generation

  17. PCAP TX Audio • Four Microphone paths supported • MICIN/MIC_OUT • AUX_MIC-/AUX_MIC+ • AUX_OUT • EXT_MIC • Two headset microphone paths • EMU connector • Barrel connector (MIC2) • Microphone paths are selected through A3_MUX, A5_MUX, EXT_MIC_MUC, and MIC2_MUX • Microphone path gain is programmable by TX PGA and MIC2 PGA • Internal microphone is a single ended surface mount part biased by MICBIAS1

  18. PCAP TX Audio

  19. PCAP RX Audio • Six audio output paths supported • SPKR+/- amplifier (Handset Earpiece Speaker) • ALERT+/- amplifier (Handset Right Loudspeaker/Alert Speaker) • PGA_OUT_L amplifier (Handset Left Loudspeaker/Alert Speaker) • ARIGHT_OUT amplifier (Headset Right Speaker) • ALEFT_OUT amplifier (Headset Left Speaker) • EXT_OUT amplifier (not used) • Stereo DAC drives the internal Left/Right PGA • Voice DAC drives the internal Right PGA only • Internal multiplexers route audio to one of six supported outputs • Handset Speaker is driven by PCAP internal SPKR differential amplifier and external class D amplifier • Headset uses mini-USB connector and 2.5mm barrel connector.

  20. PCAP RX CODEC

  21. Audio Routing • Bulverde is primary source of audio except when in a voice call • Bulverde, Neptune, and Bluetooth send digital audio to PCAP through SAP interface • Control information between Bulverde and PCAP is sent through PCAP secondary SPI • PCAP has two Digital Audio Interfaces (DAI) • DAI0 is used for voice (mono) digital audio data • DAI1 is used for stereo digital audio data

  22. Audio Routing SAP_TXD SAP_TXD GPIO [88] STDA Bulverde Neptune-LTE2 SSP-2 SAP_RXD SAP_RXD GPIO [38] SRDA SAP_FRM SAP_FRM GPIO [37] SC2A SAP_CLK SAP_CLK SCKA GPIO [50] SSP-3 SSP-1 GPIO [29] GPIO [25] GPIO [28] GPIO [26] GPIO [52] GPIO [81] GPIO [83] AP_SPI_FRM AP_SPI_CLK AP_SPI_TXD AP_SPI_RXD AP_AUD_FRM AP_AUD_RXD AP_AUD_TXD AP_AUD_CLK SAP_CLK SAP_TXD SAP_FRM AP_SPI_CS SAP_TXD SAP_RXD SAP_CLK SAP_FRM PRI_MISO PRI_SPI_CLK PRI_CE PRI_MOSI FSYNC0 TX ASAP_TX BITCLK1 FSYNC1 BITCLK0 ASAP_RX ASAP_CLK ASAP_FS RX1 RX0 Blue-Tooth BT Headset PCAP2

  23. System Clock • 26MHz Reference Clock • Derived from RF6029 • OSCM used to shut down clock when phone is in Standby • Buffered to Neptune • Used by Neptune for MCU and DSP • 32.768kHz RTC clock • Derived from RTC crystal • Buffered by PCAP to Bulverde, Neptune, and Bluetooth • Used by Neptune for low frequency peripheral interfaces • Used by Bulverde for low frequency peripheral interfaces • 13Mhz Reference Clock • Derived from 13MHz crystal for Bulverde system clock and SPI interface to PCAP • Divided from 26MHz clock in Neptune for SPI interface to PCAP

  24. 15.36MHz 26MHz System Clock

  25. Neptune LTE2 Neptune LTE2 IC derived from the Neptune LTE IC with these changes: • Increased MCU RAM size from 256Kbytes to 512Kbytes • Decreased MCU ROM size from 1.75Mbytes to 128Kbytes • The “interleaved” RAM blocks in LTE are replaced with dual-port RAM’s in order to simplify and improve the design • Parallel DMAC replaced with SLDCD smart LCD design to allow read back capability • Improved keypad interface (more columns, dual edge interrupts) • Addition of SIAC capability

  26. Neptune Block Diagram

  27. Bulverde Overview • 208MHz for the PXA270 processor • System memory interface • 100MHz SDRAM • 4MB to 256 MB of SDRAM memory • Support for 16, 64, 128, or 256Mbit DRAM technologies • 4 Banks of SDRAM, each supporting 64 MB of memory • Clock enable (CKE) – provides 1 CKE pin to put the entire SDRAM interface into self refresh • Support up to 5 external static memory devices (SRAM, flash, or VLIO) and 1 internal flash device • PCMCIA/Compact Flash card control pins • LCD Controller pins • Full-function UART • Bluetooth UART • Hardware UART • MMC Controller pins • SSP pins • Network SSP • Audio SSP • USB Client pins • AC’97 Controller pins • Standard UART pins • I2C Controller pins • PWM pins • 20 dedicated GPIOs pins • Integrated JTAG support • Single-Ended USB client

  28. Bulverde Block Diagram

  29. Battery Interface • Main Battery interface consists of 4 pin connector • Power source • Thermal sense • Battery ID contact • Ground • In normal user mode, when charger is not attached, switch M3 turned is on to support B+ the main power source. • PCAP monitors the power switch and turns on the regulators for MCU and the other main circuitry • MCU interrogates the battery identification for validity during power up sequence

  30. Battery Interface

  31. Charging System • When charger attached, EMU IC turns on M1 and M2 for charging • Charge current is regulated through 0.1 Ohm feed back via CHRGCTRL • MCU monitors battery temperature and charging current via A/D measurement from PCAP IC • If battery temperature is too high, MCU will send command via I2C bus to EMU IC to turn off charging • MCU calculates the maximum charge current allowed for the circuits before charging starts • Low rated chargers • When the MCU detects a lower rated charger or during transmit or receive of a “call” operation, the current shared mode will be selected. • In this mode, switch M1, M2, M3 will be on and M4 will be off so that maximum power can be generated to B+, the power source of the radio. • High rated chargers • When radio is in low power mode or “off” state, dual-path charge mode is selected • In dual-path charge mode, M1, M2, and M4 will be on but M3 will be off so that the battery can be charged efficiently • USB cable charging • MCU negotiates charging current with host PC • Maximum charging current is 500mA • Will operate in low battery condition • Initial charging current is under 100mA until the radio powers up

  32. Charger Block Diagram

  33. AP Memory Interface • 64M-bytes SDRAM running at 104MHz • 128M-bytes of NAND Flash memory • NOR Interface to communicate with Bulverde • Program and user memory stored in Flash • Program and data stored in Flash are copied in RAM for execution • Sub-divided Flash for boot code, OS files, and user data

  34. BP Memory Interface • 16-bit parallel data bus used to access 32Mbit Flash and 8Mbit SRAM • Each device is assigned a specific chip enable • Neptune chip select control register defines wait states for each device • Each wait state is the equivalent of one clock cycle, i.e. 1 / 13MHz = 77 ns. • Memory is a stack-memory by which both Flash and (P)SRAM are embedded into one single 8.0mm by 10mm Stacked-MSP (Chip Scale Package)

  35. Neptune Memory Interface

  36. Display • Color Active Matrix Liquid Crystal Display (AMLCD) module of glass construction with black pixels on white background • 240 (x RGB Stripe) x 320 pixels with 262K colors. • This display module is constructed of: • Has a top glass plate, top and bottom polarizers and compensation films, color filter, liquid crystal, internal transflector, a poly-Si backplane containing the pixel transistors, and row and column driving circuitry integrated onto glass • Auxiliary Backlighting System consists of white LEDs, light guide, and LED driving circuitry • FPC with LCD controller and other necessary passive components.

  37. Display Interface

  38. Display Interface

  39. Keypad • 46 key QWERTY keypad • Keypad interfaces to Bulverde • Bulverde uses 121 highly-multiplexed general-purpose I/O (GPIO) pins for capturing key entries

  40. Keypad Interface

  41. SIM Interface • PCAP supports 1.875 V or 3.0 SIMs • VSIM regulator controlled by VSIM_EN • Supply to card must be shut down before the SIM card is removed and the card loses contact with the radio • SIM module contains a block designed to generate clocks SIM module and SIM card • SIM TX block contains a transmit state machine, transmit shift register, and a transmit FIFO • SIM RX block contains a receive state machine, receive FIFO, and control logic. • On power up, the phone checks valid battery voltage and verify SIM card is present by reading data on SIM_I/O • No data indicates card not present • SIMPD input allows for detection of the insertion or removal of a SIM card

  42. SIM Interface

  43. Bluetooth • UART • 4-wire interface (Tx,Rx,RTS,CTS) • Adjustable baud rates from 9600 bps to 1.5Mbps. • Baud rate set by parameters stored in the optional EEPROM or by auto baud rate detection • AP Handshake • Bluetooth communicates with AP through GPIO • AP wakes up Bluetooth module using BT_WAKE signal • Bluetooth module wakes up AP using BT_HOST_WAKE signal • Bluetooth module is reset by AP using BT_RESET • Audio • PCM port of the Bluetooth is connected to the SAP port of the Neptune • Bluetooth audio is also connected with SSP2 port of Intel Bulverde • Power Supply • PCAP powers Bluetooth module and voltage I/O lines • BT_RF regulator powers Bluetooth core and RF section • 2.8 V I/O voltage used to power I/O signals • Clock • System clock derived from external 15.36 crystal • 32 KHz sleep clock from PCAP used during the sleep mode and auto baud rate generation

  44. Bluetooth Block Diagram