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The Devices

Dive into the intricacies of MOS transistors, gate capacitance, threshold voltage, and current-voltage relations to optimize digital design. Explore SPICE models and sub-micron transistor challenges for advanced insights.

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The Devices

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Presentation Transcript

  1. The Devices Jan M. Rabaey

  2. Goal of this chapter

  3. The MOS Transistor

  4. Cross-Section of CMOS Technology

  5. MOS transistors Types and Symbols D D G G S S Depletion NMOS Enhancement NMOS D D G G B S S NMOS with PMOS Enhancement Bulk Contact

  6. Threshold Voltage: Concept

  7. The Threshold Voltage

  8. Current-Voltage Relations

  9. Current-Voltage Relations

  10. Transistor in Saturation

  11. I-V Relation

  12. A model for manual analysis

  13. Dynamic Behavior of MOS Transistor

  14. The Gate Capacitance

  15. Average Gate Capacitance Different distributions of gate capacitance for varying operating conditions Most important regions in digital design: saturation and cut-off

  16. Diffusion Capacitance

  17. Junction Capacitance

  18. Linearizing the Junction Capacitance Replace non-linear capacitance by large-signal equivalent linear capacitance which displaces equal charge over voltage swing of interest

  19. The Sub-Micron MOS Transistor

  20. Threshold Variations

  21. Parasitic Resistances

  22. Velocity Saturation (1)

  23. Velocity Saturation (2)

  24. Sub-Threshold Conduction

  25. Latchup

  26. SPICE MODELS

  27. MAIN MOS SPICE PARAMETERS

  28. SPICE Parameters for Parasitics

  29. SPICE Transistors Parameters

  30. Fitting level-1 model for manual analysis

  31. Technology Evolution

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