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T.H.A.D.D. GROUP TOM DUAN HELEN YU ANDY LEE DANNY HUANG DAWEY HUANG

T.H.A.D.D. GROUP TOM DUAN HELEN YU ANDY LEE DANNY HUANG DAWEY HUANG. DSP Enabled Processor Design. Agenda. Datapath Design Memory Subsystem Power Optimization Performance. 5-Stage Pipeline. IF/ID PIPELINE REG. ID/EX PIPELINE REG. EX/MEM PIPELINE REG. MEM/WB PIPELINE REG. INSTRUCTION

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T.H.A.D.D. GROUP TOM DUAN HELEN YU ANDY LEE DANNY HUANG DAWEY HUANG

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  1. T.H.A.D.D. GROUPTOM DUANHELEN YUANDY LEEDANNY HUANGDAWEY HUANG DSP Enabled Processor Design

  2. Agenda • Datapath Design • Memory Subsystem • Power Optimization • Performance

  3. 5-Stage Pipeline IF/ID PIPELINE REG ID/EX PIPELINE REG EX/MEM PIPELINE REG MEM/WB PIPELINE REG INSTRUCTION CACHE REGISTER FILE DATA CACHE MAC STAGE 1 MAC STAGE 2 BRANCH LOGIC ALU JUMP LOGIC

  4. Multiply and Accumulate • 2-stage pipeline multiplier • No stalling when LW followed by MAC ID/EX PIPELINE REG EX/MEM PIPELINE REG MEM/WB PIPELINE REG REGISTER FILE MULTIPIER 1 MULTIPIER 2

  5. Critical Path (WB stage) MEM/WB PIPELINE REG 16 MAC STAGE 2 FROM DATA MEMORY 16 32 MUX 32 32 32 32 TO REGISTER FILE

  6. Memory Subsystem • 2x clock rate of processor • 3 controllers • sdram • instruction block • data block • asynchronous component interface (arbitrator)

  7. Clock Divider CLK ICLK Counter CLK2X

  8. Memory Subsystem Diagram DATA CACHE BLOCK INSTRUCTION CACHE BLOCK BUFFER MAIN CACHE VICTIM CACHE CONTROL CONTROL CACHE miss data miss data address address ARBITRATOR ready ready address SDRAM BLOCK SDRAM (GIVEN) CONTROLLER ready

  9. Cache Organization

  10. Instruction Cache/Controller ADDRESS Cache Blocks 5 BLOCKS EACH 4 WORDS Controller FSM DATA ADDRESS HIT CLK IDLE WORD READ WRITE DISABLE CHECK SDRAM READY MISS SDRAM DATA MISS SDRAM ADDRESS DOUT

  11. Data Cache

  12. Data Cache <-> Victim Cache

  13. Power Reduction Methods • Limiting VHDL sensitivity list • Balance input arrival • Enable/Disable components • Eliminate unnecessary control signals & data buses • Minimize execution time to lower supply voltage

  14. Power Consumption of Components Supply voltage = 2.5Volts

  15. Component Optimization Results (1) Supply voltage = 2.5Volts

  16. Component Optimization Results (2) Supply voltage = 2.5Volts

  17. Supply Voltage Reduction Results

  18. Supply Voltage Comparison

  19. Design Challenges • what we learned: power optimization concepts • what surprised us: component interface timing • what challenged us: reducing cache miss

  20. Conclusion • A Very Rewarding Project • Excellent Performance • Can Sleep Again!

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