Introduction

1. A 72 Channel 125 MSPS Analog-to-Digital Converter Module for Drift Chamber Readout for the GlueX Detector G. Visser1, D. Abbot2, F. Barbosa2, C. Cuevas2, H. Dong2, E. Jastrzembski2, B. Moffit2, B. Raydo2 1Indiana University Center for Exploration of Energy and Matter 2Thomas Jefferson National Accelerator Facility http://www.gluex.org/ Introduction The GlueX detector system, now under construction for Jefferson Lab Hall D includes the 3098 channel straw tube central drift chamber (CDC) surrounding the target, and the 24 layer planar cathode strip forward drift chamber (FDC) in the forward region. The FDC has 2304 anode wires with discriminator/TDC readout and 10368 cathode strips. An 8channel frontend ASIC has been developed for these detectors in TSMC 0.25 µm CMOS technology.† The CDC and the cathode strips of the FDC, a total of 13466 channels, require 12 bit ADC (waveform digitizer) readout capable of deadtimeless operation at up to 200 kHz trigger rate, providing drift time measurements with <2 ns rms error, pulse amplitude measurement for position interpolation from cathode strips in the FDC, and pulse integral measurement for dE/dx determination in both detectors. Hit rates may be up to 300 kHz in some FDC channels. The combination of maximum drift time ~1 µs and trigger rate requires a readout system capable of assigning one pulse to multiple events, an ambiguity to be resolved only later in track reconstruction. We have developed a high channel density VME64x solution for the drift chamber readout ADC, described here. It supports a sample clock up to 125 MHz. Noise and nonlinearity Features Open input: • 72 channels in a 6U VME64x/VXS module, $55 per channel • Assembly option for 12 or 14 bits • Up to 125 MSPS, internal or external sample clock • Differential input 440 mV full scale • Cable loss equalization • Shaper/anti-alias filter 24 ns peaking • Independent offset DAC per channel • Preamp test pulser output • Acquisition buffer: Dual-port circular buffer, 2048 points (19.5 μs) • FPGA-based signal processing • 1 MB buffer and 2eSST readout • Remote firmware upload (VME) Noise and linearity are evaluated with open input and with 14.9 MHz sine input. σ = 0.52 σ = 0.43 Single event 1000 pt readout σ = 5.62 (12-bit: 1.40) 11.5 ENOB Nonlinearity ≈ 0.05 % Receiver / freq eq. Crosstalk System response Preamp + 18 m cable + ADC Shaper 15 MHz* sine input, single event 100 pt readout DAC per channel ADC *Corresponds to peaking time ≈33 ns for combined system (preamp, cable, ADC) • Design choices • Some compromises are necessary for maximum channel density. The analog signal path must be kept relatively simple. • In particular: • A passive shaper uses no power, little board area • An ADC driver stage is not necessary if we can keep the drive impedance reasonably low without it • Differential drive is not necessary if the ADC uses a (relatively) high VDD and if we can tolerate a little nonlinearity • However we do not compromise on the line receiver, this is the most crucial element. It is important to: • Receive differential signal accurately • Not inject common-mode ground noise back to cable & front end electronics • Equalize cable frequency response 21 hostile (red) and 1 hostile (blue & brown) Indicates ~2% crosstalk in neighbor channels, acceptable but will try to reduce with layout improvements Mezzanine board Main board ADC FE FIFO ADC FE FIFO ADC FE FIFO • Current status • 3 modules assembled & tested • Interim firmware (FE deadtime, no block transfers) • Deployed in support of CDC and FDC development • Next steps: • Full deadtimeless readout, 2eSST transfers • Minor changed to layout (obsolence, crosstalk) • Develop production test • Pre-production run (20 modules) in early 2011 • 188 modules (+spares) in 2012 FE (Front-end processing): This includes acquisition buffer writing, point extraction, lookahead zero suppression, channel number & header insertion ADC FE FIFO … (36 ch total) … … (36 ch total) … Channel data FIFO: 1024 words (16 bits + 2 flags, internal use only) ADC FE FIFO ADC FE FIFO ADC FE FIFO ADC FE FIFO ADC FE FIFO ADC FE FIFO Each 160 MB/s i.e. 400 words/evt @ 200 kHz 320 MB/s 1 MB ADC (dual) Frontend FPGA Frontend FPGA XC3S500E-4 12 total, 6 ch each Processor FPGA Output FIFO VME slave 2eSST etc. XC3SD3400A-4 160 MB/s The bottom line… Power A linear regulator for ADC power (3.00 V @ 13 A) is impractical for this module. Solution: a low noise three phase buck converter using integrated synchronous 8A chips and an external reference and error amp. Achieves <1mV output noise and ripple. Switching frequency not detectable in ADC output noise spectrum. Measured efficiency is 89%. VME FPGA PECL/LVDS CLK & TRG input from VXS or P2 Note: Output ripple is observed mainly at the per-phase switching frequency. The imbalance ripple dominates the ideal sum ripple! Nevertheless small enough. Processing FPGA 1.026 MHz ±5.5 V supply (for receivers) 20 MHz BWL ADC PS noise/ripple <1mV Typical FDC event (preliminary data from FDC prototype) Two 10-layer boards w/ 6 planes (3 GND), 0.003” buried capacitance. Total power dissipation 58 – 68 W per module Authored by Jefferson Science Associates, LLC under U.S. DOE Contract No. DE-AC05-06OR23177. The U.S. Government retains a non-exclusive, paid-up, irrevocable, world-wide license to publish or reproduce this manuscript for U.S. Government purposes. †GAS II: A Versatile Wire Chamber Readout ASIC. N. Dressnandt, N. Doshi, M. Newcomer., IEEE NSS 2009.