NATIONAL POLYTECHNIC INSTITUTE COMPUTING RESEARCH CENTER

1. NATIONAL POLYTECHNIC INSTITUTE COMPUTING RESEARCH CENTER Design of a Multimedia Extension for RISC Processor Ing. Eduardo Jonathan Martínez Montes Ph.D. Marco Antonio Ramírez Salinas IPN-CIC MICROSE Lab

2. OUTLINE Part1 • Thesis Requirements • Committee Tutorial • Objective • Justification • Problem overview • Overview • RISC Processor • Architectures • Vector Processing • SIMD • SIMD vs SISD • Example • State of the art • Work Done • RISC Segmented Processor • Debugger • Program Memory • Data Memory • Register Alias Table • LCD Controller • UART • SRAM Controller • 2 Instruction Decode • 2 Instruction Queue IPN-CIC MICROSE Lab 2

3. OUTLINE Part 2 • Current Work • Looking for a Multiplier • Redesigning the Rename Unit • Complete the set instruction • Work as a Research Team • uClinux • Future Work • Implement a Data Bus IPN-CIC MICROSE Lab 3

4. THESIS REQUIREMENTS Committee Tutorial IPN-CIC MICROSE Lab 4

5. THESIS REQUIREMENTS Objective • General Objective • Design a multimedia extension unit for a RISC processor (Alligator). • Specific Objectives • Design a vector adder with saturation arithmetic. • Design a multiplier with saturation arithmetic. • Design a divisor with saturation arithmetic. • Implement all the Instruction set of the MIPS Digital Media extension (MDMX). IPN-CIC MICROSE Lab 5

6. THESIS REQUIREMENTS Justification Alligator is a superscalar embedded processor, now in develop. The goal of this effort is to be used to help in the research and teaching. This processor require the design and build many blocks, so that, this project is part of a bigger project. IPN-CIC MICROSE Lab 6

7. THESIS REQUIREMENTS Problem Overview • Multimedia Extension is a vector machine that is embedded in same chip with the main Superscalar Processor, it is used for deal with multimedia applications. • Integrate Multimedia Extension Architecture as a coprocessortothe Superscalar Processor • Integrate the MDMX Set Instruction as a part of ISA in the Decode stage. • Deal with memory challenges for sharing data. IPN-CIC MICROSE Lab 7

8. THESIS REQUIREMENTS Problem Overview IPN-CIC MICROSE Lab 8

9. THESIS REQUIREMENTS Problem Overview IPN-CIC MICROSE Lab 9

10. OVERVIEW RISC Processor Reduced Instruction Set Computing (RISC). The main idea is to keep the design simplified. IPN-CIC MICROSE Lab 10

11. OVERVIEW Architectures SISD: Scalar Processor, executes only one datum at a time. MIMD: Superscalar Processor, exploits parallelism in the Instruction stream. SIMD: Vector Processor, exploits parallelism in the data stream. IPN-CIC MICROSE Lab 11

12. OVERVIEW SIMD Single Instruction Multiple Data, this architecture performs the same operation on multiple data elements in parallel. IPN-CIC MICROSE Lab 12

13. OVERVIEW SIMD vs SISD IPN-CIC MICROSE Lab 13

14. OVERVIEW SIMD Example (part 1) Example: get negative image IPN-CIC MICROSE Lab 14

15. OVERVIEW SIMD Example (part 2) Normal Processing IPN-CIC MICROSE Lab 15

16. OVERVIEW SIMD Example (Part 3) Parallel Processing IPN-CIC MICROSE Lab 16

17. OVERVIEW State of the Art AltiVec - IBM 1996 2002 SSE4 - Intel Pentium II (MMX)- Intel 2006 Sandy Bridge y Bulldozer - Intel y AMD 1998 3DNow!. - AMD SSE3 - Intel 2000 2004 2011 1996 1998 2000 2002 2004 2006 2008 2010 2012 2002 2008 2013 1997 SSE2 - Intel Advanced Vector Extensions (AVX) - Intel AVX2 - Intel AltiVec - Motorola 2004 1999 SSE y SSE2 - AMD Streaming SIMD Extensions (SSE)- Intel 1996 2003 Advance 3DNow! (3DNow! 2) - AMD IPN-CIC MICROSE Lab 17

18. WORK DONE RISC Segmented Processor IPN-CIC MICROSE Lab 18

19. WORK DONE Debugger (part 1) Definition Every time that you create something new, like a program or in this case new hardware. You need something to test and trace faults and then fix it. All the developers, even all the engineers know what a debugger tool. IPN-CIC MICROSE Lab 19

20. WORK DONE Debugger (part 2) • Features • Friendly GUI interface • Load and download the Program Memory • Load and download the Data Memory • View the registers • Reset the processor • Pause the processor • Run step by step de processor • Use breakpoints • Change the clock frequency • In fact, it can work without a GUI! IPN-CIC MICROSE Lab 20

21. WORK DONE Debugger (part 3) IPN-CIC MICROSE Lab 21

22. WORK DONE The Program Memory (cache L1) • Implemented in dedicated memory (M9K) • 1 write port • 2 read port • Size 512 bytes IPN-CIC MICROSE Lab 22

23. WORK DONE The Data Memory (cache L1) • Implemented in dedicated memory (M9K) • 2 write port • 5 read port • Size 512 bytes IPN-CIC MICROSE Lab 23

24. WORK DONE Register Alias Table • Implemented in dedicated memory • 6 write port • 12 read port • 128 register of 32 bits IPN-CIC MICROSE Lab 24

25. WORK DONE LCD Controller • It has a state machine that read a 32 register memory (32x8) • Characters are only write in the memory and it does the rest IPN-CIC MICROSE Lab 25

26. WORK DONE UART • 9600 bps • 8N1 IPN-CIC MICROSE Lab 26

27. WORK DONE SRAM Controller IPN-CIC MICROSE Lab 27

28. WORK DONE Two Instruction Decode IPN-CIC MICROSE Lab 28

29. WORK DONE Two Instruction Queue • Implemented in dedicated memory • 2 write port • 2 read port • 16 register • Circular Queue IPN-CIC MICROSE Lab 29

30. CURRENT WORK Looking for a Multiplier • Fast • Signed • Unsigned IPN-CIC MICROSE Lab 30

31. CURRENT WORK Looking for a Multiplier IPN-CIC MICROSE Lab 31

32. WORK AS A RESEARCH TEAM Booting uClinux Booting uClinux in Alligator Processor IPN-CIC MICROSE Lab 32

33. FUTURE WORK Data Bus (part 1) SRAM controller SDRAM controller Flash controller Flash controller UART controller LCD controller IPN-CIC MICROSE Lab 33

34. FUTURE WORK Data Bus (part 2) IPN-CIC MICROSE Lab 34

35. Q&A IPN-CIC MICROSE Lab 35