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Data Aligner

This project addresses the critical issue of high-speed data transfer in serial communication, focusing on the synchronization and alignment of data during de-serialization. A solution is proposed by implementing a protocol layer over the physical layer, utilizing pre-defined symbols for accurate communication. The firmware is developed in VHDL with generics, achieving reliable data alignment at a frequency of 125 MHz on a Cyclone II FPGA. The software includes a user-friendly MATLAB GUI for debugging, real-time status indication, and analysis of data integrity, ensuring robust communication with the FPGA.

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Data Aligner

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Presentation Transcript

  1. Data Aligner Poster Tomer Ofir Omri Glaser Supervisor: Moshe Porian March 2012

  2. Abstract Serial communication has a major role in to High-Speed data transfer. Later, data are being de-serialized into parallel form. However, without handshake, destructive synchronization & alignment problem may occur.

  3. Solution: Implement protocol layer over physical layer, and use pre-defined symbols to synchronize and align data

  4. Specification Firmware: • VHDL implementation with generics for protocol parameters • Announce synchronization • Produce aligned data reliably • Achieve goals at frequency of 125MHZ using cyclone II Software: • GUI implementation of user-friendly debug envinroment • Communication with FPGA via UART

  5. Block Diagram

  6. MATLAB GUI Pass / Fail indication Status of test progress Insert planned errors for stimulus Insert generic values Preview & Run Buttons Here appears the hexadecimal representation of the stimulus (sent), received and expected vectors This graphs illustrates which packets are “good” in the stimulus to UUT Choose packet to show its binary representation Here is shown the binary representation (not shifted) of the packet whose number is chosen above This graphs describes the distribution of the size of packets sent to UUT A table that describes the size of each packet in the stimulus

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