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Testimise projekteerimine: Labor 2 BIST Optimization

Explore the benefits and drawbacks of Built-in Self-Test (BIST) for memory circuits, including fault coverage, test generation cost, and performance overhead.

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Testimise projekteerimine: Labor 2 BIST Optimization

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  1. Testimise projekteerimine:Labor 2BIST Optimization Sergei Kostin

  2. BIST (Built-in Self Test) BIST Control Unit Test Pattern Generator (PRPG) ........ BIST Memory Circuit Under Test (CUT) ........ Output Response Analyzer (MISR) ehk sisseehitatud isetestimineon digitaalskeemi(mikroskeemi, plaadi, süsteemi jms) omadus iseennast testida. Typical BIST Architecture

  3. Built-In Self-Test • Motivations for BIST: • Need for a cost-efficient testing(general motivation) • Doubts about the stuck-at fault model • Increasing difficulties with TPG (Test Pattern Generation) • Growing volume of test pattern data • Cost of ATE (Automatic Test Equipment) • Test application time • Gap between tester and UUT (Unit Under Test) speeds • Drawbacks of BIST: • Additional pins and silicon area needed • Decreased reliability due to increased silicon area • Performance impact due to additional circuitry • Additional design time and cost

  4. BIST Benefits • Faults tested: • Single stuck-at faults • Delay faults • Single stuck-at faults in BIST hardware • BIST benefits • Reduced testing and maintenance cost • Lower test generation cost • Reduced storage / maintenance of test patterns • Simpler and less expensive ATE • Can test many units in parallel • Shorter test application times • Can test at functional system speed

  5. Economics – BIST Costs • Chip area overhead for: • Test controller • Hardware pattern generator • Hardware response compacter • Testing of BIST hardware • Pin overhead -- At least 1 pin needed to activate BIST operation • Performance overhead – extra path delays due to BIST • Yield loss – due to increased chip area or more chips In system because of BIST • Reliability reduction – due to increased area • Increased BIST hardware complexity – happens when BIST hardware is made testable

  6. BIST: Exhaustive test Universal test sets 1. Exhaustive test (trivial test) 2. Pseudo-exhaustive test Properties of exhaustive tests 1. Advantages (concerning the stuck at fault model): - test pattern generation is not needed - fault simulation is not needed - no need for a fault model - redundancy problem is eliminated - single and multiple stuck-at fault coverage is 100% - easily generated on-line by hardware 2. Shortcomings: - long test length (2n patterns are needed, n - is the number of inputs) - CMOS stuck-open fault problem

  7. Problems with BIST: Hard to Test Faults Fault Coverage Time The main motivations of using random patterns are: - low test generation cost - high initial efficiency Problem: Low fault coverage Pseudo-random test window: Patterns from LFSR: 2n-1 1 Hard to test faults Dream solution: Find LFSR such that: 2n-1 1 Hard to test faults

  8. Problems with Pseudo-Random Test Fault Coverage Time Problem:low fault coverage The main motivations of using random patterns are: - low generation cost - high initial efeciency & 1 LFSR Decoder Counter Reset If Reset = 1 signal has probability 0,5 then counter will not work and 1 for AND gate may never be produced

  9. Pseudo-Random Test Generation by LFSR Fault Coverage Fault Coverage Time Time breakpoint Problems: • Very long test application time • Low fault coverage • Area overhead • Additional delay Possible solutions • Weighted pattern PRPG • Combining pseudo-random test with deterministic test • Hybrid BIST • Multiple seed (Reseeding)

  10. Hybrid test set contains pseudo-random and deterministic vectors Pseudo-random test is improved by a stored test set which is specially generated to target the random resistant faults Optimization problem: Hybrid Built-In Self-Test Pseudo-random Test Determ. Test Deterministic patterns Pseudo-random patterns Where should be this breakpoint?

  11. Hybrid BIST Technique PR (pseudo-random patterns) ATP (deterministic patterns) seed / poly 100% 100% 100%

  12. BIST Optimization Challenges ATPG curve ATPG patterns from memory slow growth section fast growth section Fault Coverage (%) PRPG curve Time (clk)

  13. Reseeding (Multiple Seeds) The main motivations of using random patterns are: - low generation cost - high initial efeciency Problem: low fault coverage long PR test Pseudo-random test: 2n-1 1 Hard to test faults Solution:many seeds Pseudo-random test: 2n-1 1

  14. Reseeding Optimization Problem Pseudo-random sequences: Pseudo-random test: Using many seeds: Seed 1 2n-1 1 L Seed 2 Block size: Problems: How to calculate the number and size of blocks? Which deterministic patterns should be the seeds for the blocks? MinimizeL at given Mand100% FC Deterministic test (seeds): 100% FC M Seed 1 Seed 2 Constraints Seed n Seed n

  15. Cost Calculation for Hybrid BIST Pseudorandom Test Det. Test CTOTAL = T + M(k) # faults not detected # tests needed PR test length Cost T M(k) min CTOTAL

  16. Variant 5

  17. ISCAS’ 85 benchmark circuit

  18. Task 1: Pseudo-random test generation • Find out the maximum fault coverage for given circuits applying tuned ATPG. • Algorithms  New = ATPG ATPG (Automated Test Pattern Generator) • Genetic • Deterministic • Random • ATPG algorithms description: • Turbo Tester v02.10.pdf (edu.pld.ttu.ee  minumaterjalid) • 4.2 Test Pattern Generation

  19. Task 1: Pseudo-random test generation • Choose “good” seed and polynomial to generate effective pseudo-random test. • “good” polynomial: random or primitive • “good” seed: pattern testing HTTF (hard-to-test faults) (select from ATPG test)

  20. Task 1: Pseudo-random test generation • Pseudo-random test sequence must have • maximum fault coverage (same as for ATPG) • length of test must be in the range T<= length<=1,2T where T – Time Constraint from Table 2. • Example: c1908  T = 7500 and 1,2T = 1,2*7500 = 9000  7500 <= test length <= 9000 • Hint: When generating a test put the number of clock cycles equal to 1,2T • if maximum fault coverage achieved within given test then cut out last patterns that do not give additional fault coverage • Use Type I and Type II generators. • Fill in the table

  21. Task 2 and 3 • Reseeding algorithm: • Find complete test (max. fault coverage) for given circuit, using the best PRPG (Type I LFSR) test sequence achieved in task 1. • Perform experiments stepping through the constraint values and choose 5 results (test must comply with the constraints specified in your variant). Example: c1908 M = 1, 2, 3…10 (min.step = 1); T = 7500, 7000, 6500… (min.step = at least 5% of T). • Hybrid BIST algorithm: • Find complete test (max. fault coverage) for given circuit, using the best PRPG (Type I LFSR) test sequence achieved in task 1. • Perform experiments and choose 5 evenly distributed results (test must comply with the constraints specified in your variant).

  22. Reseeding and Hybrid Algorithms • PRPG • Load  use saved sequence of pseudo-random test patterns • Sync  use generated in PRPG panel sequence of test patterns • Constraint • Time  test length (number of pseudo-random test patterns) • Memory (vectors)  number of deterministic test patterns stored in memory

  23. Reseeding and Hybrid Algorithms • Load model (AGM panel) • Load or Sync PR test (PRPG panel) • Generate ATPG test (press New or Load button) • Select Time or Memory(vectors ) Constraint and enter the constraint • Run In order to Run Reseeding or Hybrid Algorithm with another constraint: just change constraint and press Run

  24. Reseeding: calculating BIST cost Test Length (T) = 3770, FV = 99,48% Block size = 377  M = 3770/377 – 1 = 9 Cost = 3770 + 400*9 = 7370

  25. Hybrid: calculating BIST cost M = 10, FV = 99,48% Test Length (T) = 2887 + 10 = 2897, Cost = 2897 + 400*10 = 6897

  26. Fill in the Result Table Circuit 1: C1908 • Memory Constraint: min. step is 1 • Example: c1908 constraint = 15  M = 1,2,3,...,15 • Time Constraint: min. step is at least 5% of constraint and number of memory vectors must change • Example: c1908 constraint = 7500  T = 7500, 7000, 6500... • NB! if cannot find 5 satisfactory tests for Reseeding, decrease • min. step or use Memory constraint instead • NB! Try to use the same constraints for both algorithms  this helps to compare effectiveness of Reseeding and Hybrid algorithms

  27. Task 4 • Results evaluation: • According to the marginal results obtained in task 2 and 3 construct the Cost curves on the same graph for Reseeding and Hybrid BIST algorithms. • Compare results of Reseeding and Hybrid algorithms.

  28. BIST Cost Curves for Circuit c1908

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