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先进测试助力“中国芯”. 上海华岭集成电路技术股份有限公司. Overview. Founded in 2001; Shanghai Zhang Jiang Hi-Tech Park; Company area 4000M 2 , Clean room 2000M 2 ; Employee: 100+, Engineer: 40+; Test program development; probe card / Load board design & layout; 8-12 inch wafer probing; Final test;. Clean room.
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先进测试助力“中国芯” 上海华岭集成电路技术股份有限公司
Overview • Founded in 2001; Shanghai Zhang Jiang Hi-Tech Park; • Company area 4000M2, Clean room 2000M2; • Employee: 100+, Engineer: 40+; • Test program development; probe card / Load board design & layout; • 8-12 inch wafer probing; • Final test; Sino IC Technology Co.,Ltd.
Clean room • 2000m2 clean room Sino IC Technology Co.,Ltd.
Test engineering service Sino IC Technology Co.,Ltd.
Remote connection Sino IC Technology Co.,Ltd.
Test capacity Sino IC Technology Co.,Ltd.
Product type RF ICs (Bluetooth,Tuner,PA,RFID) Memory ICs (Flash,SRAM,EEPROM) MOSFET ICs (600-1000V,1-20A) SoC ICs (CPU,DSP,FPGA) PM ICs (LDO,PWM,DC-DC) Mixed signal ICs (MCU,Demodulator,ADC/DAC) Sino IC Technology Co.,Ltd.
Test system Sino IC Technology Co.,Ltd.
Tester configuration • Ultra FLEX (High end SoC tester ) • RF:Max. 12GHz • Serial high speed: • Max. 6.4GHz • Digital channel:1GHz • Power supply: • DC30、DC75、HDVS • Option: • BBAC、TurboAC、VHFAC Sino IC Technology Co.,Ltd. 9
Tester configuration cont. • J750EX Test channel: 512 - 1024 • Test rate: 200MHz • Option: ADC/DAC/Memory • J750 Test channel: 256 - 512 • Test frequency: 100MHz • Option: ADC/DAC/RFID • V50 Test channel: 128 - 256 • Test frequency: 50MHz • Option: Mixed signal Sino IC Technology Co.,Ltd. 10
Prober configuration • UF3000 Wafer size: 300/200mm • Test temp.: -40oC - +150oC • UF200A Wafer size: 200/150mm • Test temp.: -40oC - +150oC • UF200R Wafer size: 200/150mm • Wafer thickness: Min 90um • P8XL/P8 Wafer size: 200-100mm Sino IC Technology Co.,Ltd. 11
Partners Foundry & Assembly Vendor & Supplier Sino IC Technology Co.,Ltd.
Test Plan Device setup Pilot run (1-3 Lot) Program Coding VCD conversion Debugging Program validation Load board/ Probe card Data correlation Program release Development flow 1-2 weeks 1 week Cycle time: 2 weeks Sino IC Technology Co.,Ltd.
IQC Run correlation wafer Offline ink Run card OQC Wafer probing (OD,yield) Test set up (program, OD,temp.) FTP data (wafer map, datalog) Packing/ shipment Testing flow Sino IC Technology Co.,Ltd.