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Prediction and Control of Instruction Sequences in Pipelined Processors

Learn about key strategies like Predict Not Taken, Predict Taken, and Delayed Branch for managing instruction flow in pipelines efficiently. Discover hardware and software advantages of each method.

joelle-harmon
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Prediction and Control of Instruction Sequences in Pipelined Processors

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  1. Predicción de saltos

  2. Stall pipeline • Es el esquemamas simple paramanejar los saltos. HacerFreeze o flush del pipeline, detener o borrarcualquierinstrucciondespues del branch hastaque el destino del branch sea determinado. Ventaja: simple en Hardware y Software.

  3. Predict Not Taken • Unamejor performance, y solo un pocomascompleja. La idea espredecirsiempre el saltocomo NO TOMADO. El hardware continua cargandolasintruccionescomosi el branch no fueratomado. • Se debetenercuidad de no cambiar la maquina de estados (UC – PC) hastaque el salto sea determinadofeacientemente • La complejidad se basa en: se debepoderimplementar un “vueltaatras” porsi el salto se toma.

  4. Predict Not Taken

  5. PredictTaken • Un esquemaalternativoespredecir el branch comosiempretomado. • Tan pronto como el branch esdecodificado se calcula la dirección de la nuevainstrucción y continuando, desdeesenuevopunto.

  6. DelayedBranch • En un saltodemorado, el ciclo de ejecución con un salto de longitud n Branch instrsequential successor 1sequential successor 2. . . . .sequential successor n Los sucesoressecuencialesestan en losbranch-delay slots. Estasinstrucciones son ejecutadas sin importarsi se toma o no el salto.

  7. DelayedBranch

  8. DelayedBranch (compilador) • EL trabajo del compiladoreshacerque la sucesión de instrucciones sea valida y útil.Existen 3 esquemasparapredecir: From before branch From target From fall through

  9. DelayedBranch

  10. En Intel asymmetric design in the Pentium: The state follows the +arrows when the branch instruction jumps, and the -arrows when not jumping. The branch instruction is predicted to jump next time if in state 2 or 3, and to not jump when in state 0 or 1.

  11. En Intel II symmetric design: This is how the branch prediction should work. The state is incremented when jumping (+arrows) and decremented when not jumping (-arrows).

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