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Topological Design of Clock Distribution Networks with Non-Zero Clock Skew Specifications

This paper presentation, delivered by Shaobo Liu at the University of Michigan, explores innovative techniques in the design of clock distribution networks, focusing on non-zero clock skew specifications. Key topics include the determination of clock path delay, theoretical background, algorithms for clock path delay, and the topology of clock distribution networks. The research emphasizes optimizing clock skew to enhance circuit performance through hierarchical representation and clock tree structures. This work presents significant findings that inform future designs of high-speed networks for better delay management.

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Topological Design of Clock Distribution Networks with Non-Zero Clock Skew Specifications

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  1. EECS 527 Paper Presentation Topological Design of Clock Distribution Networks Based on Non-Zero Clock Skew Specifications - by Jose Luis Neves and Eby G. Friedman Presented by Shaobo Liu Department Electrical Engineering and Computer Science University of Michigan, Ann Arbor 04/2013

  2. EECS 527 Paper Presentation • Outlines • Introduction • Determination of Clock Path Delay • Theoretical background • Clock Path Delay Algorithm • Topology of Clock Distribution Network • Construction of the Clock Tree Structure • Calculation of Branch Delay • Reorganization of the Clock Tree • Results • Summary • Q & A

  3. Introduction • Several techniques • Repeater Insertion • Convert highly resistive-capacitive networks into effectively capacitive networks • H-tree structures • Symmetric distribution networks • Ensure minimal clock skew • Zero skew clock routing algorithms • Automatically layout these high speed networks in cell-based designs

  4. Introduction • Two fundamental properties of clock distribution networks • Clock skew is only meaningful between sequentially adjacent register • Clock skew can be used to improve circuit performance by evening out the delay between slow and fast path

  5. Introduction • Clock Skew Description • Negative • If the clock delay to the initial register is less than the clock delay tothe final register • Positive • If the clock delay to the initial register is greater than the clock delayto the final register

  6. Determination of Clock Path Delay • Theoretical Background • Definition 1 • Given two sequentially adjacent registers, Ri and Rj • The clock skew between these two registers is defined as • TCDi: Clock delays from the clock source to the register Ri • TCDj: Clock delays from the clock source to the register Rj

  7. Determination of Clock Path Delay • Theoretical Background • More Definition • Local data path • The path between two sequentially adjacent registers • Global data path • Consist of one or more local data path

  8. Determination of Clock Path Delay • Theoretical Background • Theorem 1 • For any given global data path, clock skew is conserved • The clock skew between any two registers which are not necessary adjacent • Sum of the clock clock skew between each pair of registers along theglobal data path between those two same registers • Extends Definition 1 • Any non-sequentially adjacent registers belong to the same globaldata path • Clock skew between two registers not belong to the same global datapath has no physical meaning

  9. Determination of Clock Path Delay • Theoretical Background • Circuits may contain sequential feedback paths • The relation between feedback and forward path is formalized

  10. Determination of Clock Path Delay • Theoretical Background • Theorem 2 • For any given global data path containing feedback paths • Clock skew in feedback path between any two registers, Rland Rj • Relate to the clock skew of the forward path by the following relationship

  11. Determination of Clock Path Delay • Clock path delay algorithm • Circuits for this paper

  12. Determination of Clock Path Delay • Clock path delay algorithm • Optimal delay assignment for the data path example

  13. Determination of Clock Path Delay • Clock path delay algorithm • Algorithm Path Delay

  14. Determination of Clock Path Delay • Clock path delay algorithm • Clock distribution network

  15. Topology of Clock Distribution Network • Construction of the clock tree structure • Hierarchical representation of the data path example

  16. Topology of Clock Distribution Network • Calculation of branch delay • Two characteristics of the hierarchical representation • The clock skew between sequentially adjacent registers may not depend on the delay of the internal branches • The clock skew specifications may be satisfied if the delay of some of the internal branches is known

  17. Topology of Clock Distribution Network • Calculation of branch delay • Three steps to determine the individual branch delays • Delay of External Branches • Delay of Internal Branches • Delay Shifting

  18. Topology of Clock Distribution Network • Calculation of branch delay • Delay assignment for each branch of the example

  19. Topology of Clock Distribution Network • Reorganization of the clock tree • Delay assignment for non-hierarchically defined clock distribution network

  20. Results • Minimum clock delay and total number of delay units for several example circuits

  21. Summary • Determination of Clock Path Delay • Theoretical Background • Clock Path Delay Algorithm • Topology of Clock Distribution Network • Construction of the Clock Tree Network • Calculation of Branch Delay • Reorganization of the Clock Tree • Future Research • Determine the Optimal Non-zero Clocking Characteristics • Design of Circuits Structure to Emulate Delay values of the Network Branches

  22. EECS 527 Paper Presentation • Thanks! • Q & A

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