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High Performance Embedded Computing Software Initiative (HPEC-SI)

High Performance Embedded Computing Software Initiative (HPEC-SI). Dr. Jeremy Kepner / Lincoln Laboratory

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High Performance Embedded Computing Software Initiative (HPEC-SI)

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  1. High Performance Embedded ComputingSoftware Initiative (HPEC-SI) Dr. Jeremy Kepner / Lincoln Laboratory This work is sponsored by the Department of Defense under Air Force Contract F19628-00-C-0002. Opinions, interpretations, conclusions, and recommendations are those of the author and are not necessarily endorsed by the United States Government.

  2. Outline • Goals • Program Structure • Introduction • Demonstration • Development • Applied Research • Future Challenges • Summary

  3. Overview - High Performance Embedded Computing (HPEC) Initiative DARPA HPEC Software Initiative Applied Research Development Demonstration Programs Enhanced Tactical Radar Correlator (ETRAC) Common Imagery Processor (CIP) Embedded multi-processor Shared memory server ASARS-2 Challenge: Transition advanced software technology and practices into major defense acquisition programs

  4. Why Is DoD Concerned with Embedded Software? Source: “HPEC Market Study” March 2001 Estimated DoD expenditures for embedded signal and image processing hardware and software ($B) • COTS acquisition practices have shifted the burden from “point design” hardware to “point design” software • Software costs for embedded systems could be reduced by one-third with improved programming models, methodologies, and standards

  5. Issues with Current HPEC Development Inadequacy of Software Practices & Standards Predator U-2 Global Hawk MK-48 Torpedo JSTARS MSAT-Air Rivet Joint F-16 Standard Missile P-3/APS-137 NSSN AEGIS System Development/Acquisition Stages 4 Years 4 Years 4 Years Program Milestones System Tech. Development System Field Demonstration Engineering/ manufacturing Development Insertion to Military Asset Signal Processor Evolution 1st gen. 3rd gen. 2nd gen. 4th gen. 5th gen. 6th gen. • High Performance Embedded Computing pervasive through DoD applications • Airborne Radar Insertion program • 85% software rewrite for each hardware platform • Missile common processor • Processor board costs < $100k • Software development costs > $100M • Torpedo upgrade • Two software re-writes required after changes in hardware design Today – Embedded Software Is: • Not portable • Not scalable • Difficult to develop • Expensive to maintain

  6. Evolution of Software Support Towards“Write Once, Run Anywhere/Anysize” COTS development DoD software development Application Application Application Application Middleware • Application software has traditionally been tied to the hardware Middleware Embedded Standards Vendor Software Vendor Software Vendor Software • Many acquisition programs are developing stove-piped middleware “standards” Vendor SW 1990 2000 2005 • Open software standards can provide portability, performance, and productivity benefits Application Application Application Middleware • Support “Write Once, Run Anywhere/Anysize”

  7. Quantitative Goals & Impact Demonstrate Portability (3x) Productivity (3x) Object Oriented Open Standards HPEC Software Initiative Interoperable & Scalable Prototype Develop Performance (1.5x) Program Goals • Develop and integrate software technologies for embedded parallel systems to address portability, productivity, and performance • Engage acquisition community to promote technology insertion • Deliver quantifiable benefits Portability:reduction inlines-of-code to change port/scale to new system Productivity:reduction in overall lines-of-code Performance:computation and communication benchmarks

  8. Organization Executive Committee Technical Advisory Board Dr. Charles Holland PADUSD(S+T) … Dr. Rich Linderman AFRL Dr. Richard Games MITRE Mr. John Grosh OSD Mr. Bob Graybill DARPA/ITO Dr. Keith Bromley SPAWAR Dr. Mark Richards GTRI Dr. Jeremy Kepner MIT/LL Demonstration Development Applied Research Advanced Research Government Lead Dr. Keith Bromley SPAWAR Dr. Richard Games MITRE Dr. Jeremy Kepner, MIT/LL Mr. Brian Sroka MITRE Mr. Ron Williams MITRE ... Dr. James Lebak MIT/LL Dr. Mark Richards GTRI Mr. Dan Campbell GTRI Mr. Ken Cain MERCURY Mr. Randy Judd SPAWAR ... Mr. Bob Bond MIT/LL Mr. Ken Flowers MERCURY Dr. Spaanenburg PENTUM Mr. Dennis Cottel SPAWAR Capt. Bergmann AFRL Dr. Tony Skjellum MPISoft ... Mr. Bob Graybill DARPA Dr. Rich Linderman AFRL • Partnership with ODUSD(S&T), Government Labs, FFRDCs, Universities, Contractors, Vendors and DoD programs • Over 100 participants from over 20 organizations

  9. HPEC-SI Capability Phases • First demo successfully completed • SeconddDemo Selected • VSIPL++ v0.8 spec completed • VSIPL++ v0.2 code available • Parallel VSIPL++ v0.1 spec completed • High performance C++ demonstrated Time Phase 3 Applied Research: Hybrid Architectures Phase 2 Development: Fault tolerance Applied Research: Fault tolerance prototype Phase 1 Demonstration: Unified Comp/Comm Lib Applied Research: Unified Comp/Comm Lib Development: Unified Comp/Comm Lib Parallel VSIPL++ prototype Development: Object-Oriented Standards Demonstration: Object-Oriented Standards VSIPL++ Functionality Parallel VSIPL++ Demonstration: Existing Standards • Unified embedded computation/ communication standard • Demonstrate scalability VSIPL++ VSIPL MPI • High-level code abstraction (AEGIS) • Reduce code size 3x • Demonstrate insertions into fielded systems (CIP) • Demonstrate 3x portability

  10. Outline • Common Imagery Processor • AEGIS BMD (planned) • Introduction • Demonstration • Development • Applied Research • Future Challenges • Summary

  11. Common Imagery Processor - Demonstration Overview - Common Imagery Processor (CIP) is a cross-service component TEG and TES Sample list of CIP modes • U-2 (ASARS-2, SYERS) • F/A-18 ATARS (EO/IR/APG-73) • LO HAE UAV (EO, SAR) • System Manager 38.5” CIP* ETRAC JSIPS-N and TIS JSIPS and CARS * CIP picture courtesy of Northrop Grumman Corporation

  12. Common Imagery Processor - Demonstration Overview - APG 73 SAR IF • Demonstrate standards-based platform-independent CIP processing (ASARS-2) • Assess performance of current COTS portability standards (MPI, VSIPL) • Validate SW development productivity of emerging Data Reorganization Interface • MITRE and Northrop Grumman Embedded Multicomputers Common Imagery Processor Single code base optimized for all high performance architectures provides future flexibility Shared-Memory Servers Commodity Clusters Massively Parallel Processors

  13. Software Ports Embedded Multicomputers • CSPI - 500MHz PPC7410 (vendor loan) • Mercury - 500MHz PPC7410 (vendor loan) • Sky - 333MHz PPC7400 (vendor loan) • Sky - 500MHz PPC7410 (vendor loan) Mainstream Servers • HP/COMPAQ ES40LP - 833-MHz Alpha ev6 (CIP hardware) • HP/COMPAQ ES40 - 500-MHz Alpha ev6 (CIP hardware) • SGI Origin 2000 - 250MHz R10k (CIP hardware) • SGI Origin 3800 - 400MHz R12k (ARL MSRC) • IBM 1.3GHz Power 4 (ARL MSRC) • Generic LINUX Cluster

  14. Portability: SLOC Comparison ~1% Increase ~5% Increase Sequential VSIPL Shared Memory VSIPL DRI VSIPL

  15. Shared Memory / CIP Server versus Distributed Memory / Embedded Vendor Latency requirement Shared memory limit for this Alpha server Application can now exploit many more processors, embedded processors (3x form factor advantage) and Linux clusters (3x cost advantage)

  16. Form Factor Improvements Current Configuration Possible Configuration IOP IOP IFP1 6U VME IFP2 • IOP: 6U VME chassis (9 slots potentially available) • IFP: HP/COMPAQ ES40LP • IOP could support 2 G4 IFPs • form factor reduction (x2) • 6U VME can support 5 G4 IFPs • processing capability increase (x2.5)

  17. HPEC-SI Goals1st Demo Achievements Portability:zero code changes required Productivity:DRI code 6x smaller vs MPI (est*) Performance:2x reduced cost or form factor Demonstrate Achieved Goal 3x Portability Achieved* Goal 3x Productivity Object Oriented Open Standards HPEC Software Initiative Portability:reduction inlines-of-code to change port/scale to new system Productivity:reduction in overall lines-of-code Performance:computation and communication benchmarks Interoperable & Scalable Prototype Develop Performance Goal 1.5x Achieved

  18. Outline • Object Oriented (VSIPL++) • Parallel (||VSIPL++) • Introduction • Demonstration • Development • Applied Research • Future Challenges • Summary

  19. Emergence of Component Standards System Controller Node Controller Parallel Embedded Processor Data Communication:MPI, MPI/RT, DRI Control Communication:CORBA, HP-CORBA P0 P1 P2 P3 HPEC Initiative - Builds on completed research and existing standards and libraries Consoles Other Computers Computation: VSIPL VSIPL++, ||VSIPL++ Definitions VSIPL = Vector, Signal, and Image Processing Library ||VSIPL++ = Parallel Object Oriented VSIPL MPI = Message-passing interface MPI/RT = MPI real-time DRI = Data Re-org Interface CORBA = Common Object Request Broker Architecture HP-CORBA = High Performance CORBA

  20. VSIPL++ Productivity Examples BLAS zherk Routine • BLAS = Basic Linear Algebra Subprograms • Hermitian matrix M: conjug(M) = Mt • zherk performs a rank-k update of Hermitian matrix C: C a A  conjug(A)t + b C • VSIPL code A = vsip_cmcreate_d(10,15,VSIP_ROW,MEM_NONE); C = vsip_cmcreate_d(10,10,VSIP_ROW,MEM_NONE); tmp = vsip_cmcreate_d(10,10,VSIP_ROW,MEM_NONE); vsip_cmprodh_d(A,A,tmp); /* A*conjug(A)t */ vsip_rscmmul_d(alpha,tmp,tmp);/* a*A*conjug(A)t */ vsip_rscmmul_d(beta,C,C); /* b*C */ vsip_cmadd_d(tmp,C,C); /* a*A*conjug(A)t + b*C */ vsip_cblockdestroy(vsip_cmdestroy_d(tmp)); vsip_cblockdestroy(vsip_cmdestroy_d(C)); vsip_cblockdestroy(vsip_cmdestroy_d(A)); • VSIPL++ code (also parallel) Matrix<complex<double> > A(10,15); Matrix<complex<double> > C(10,10); C = alpha * prodh(A,A) + beta * C; • Sonar Example • K-W Beamformer • Converted C VSIPL to VSIPL++ • 2.5x less SLOCs

  21. Results Hand coded loop achieves good performance, but is problem specific and low level Optimized VSIPL performs well for simple expressions, worse for more complex expressions PETE style array operators perform almost as well as the hand-coded loop and are general, can be composed, and are high-level PVL PowerPC AltiVec Experiments A=B+C A=B+C*D+E*F A=B+C*D A=B+C*D+E/F Software Technology AltiVec loop VSIPL (vendor optimized) PETE with AltiVec • C • AltiVec aware VSIPro Core Lite • (www.mpi-softtech.com) • No multiply-add • Cannot assume unit stride • Cannot assume vector alignment • C++ • PETE operators • Indirect use of AltiVec extensions • Assumes unit stride • Assumes vector alignment • C • For loop • Direct use of AltiVec extensions • Assumes unit stride • Assumes vector alignment

  22. Parallel Pipeline Mapping Mapping Parallel Computer Signal Processing Algorithm Filter XOUT = FIR(XIN ) Beamform XOUT = w *XIN Detect XOUT = |XIN|>c • Data Parallel within stages • Task/Pipeline Parallel across stages

  23. Scalable Approach A = B + C A = B + C Single Processor Mapping #include <Vector.h> #include <AddPvl.h> void addVectors(aMap, bMap, cMap) { Vector< Complex<Float> > a(‘a’, aMap, LENGTH); Vector< Complex<Float> > b(‘b’, bMap, LENGTH); Vector< Complex<Float> > c(‘c’, cMap, LENGTH); b = 1; c = 2; a=b+c; } Multi Processor Mapping • Single processor and multi-processor code are the same • Maps can be changed without changing software • High level code is compact Lincoln Parallel Vector Library (PVL)

  24. Outline • Fault Tolerance • Parallel Specification • Hybrid Architectures (see SBR) • Introduction • Demonstration • Development • Applied Research • Future Challenges • Summary

  25. Dynamic Mapping for Fault Tolerance Map2 Nodes: 1,3 Failure Spare Map1 Nodes:0,2 XOUT XIN Map0 Nodes: 0,1 Output Task Input Task Parallel Processor • Switching processors is accomplished by switching maps • No change to algorithm required • Developing requirements for ||VSIPL++

  26. Parallel Specification Clutter Calculation (Linux Cluster) % Initialize pMATLAB_Init; Ncpus=comm_vars.comm_size; % Map X to first half and Y to second half. mapX=map([1 Ncpus/2],{},[1:Ncpus/2]) mapY=map([Ncpus/2 1],{},[Ncpus/2+1:Ncpus]); % Create arrays. X = complex(rand(N,M,mapX),rand(N,M,mapX)); Y = complex(zeros(N,M,mapY); % Initialize coefficents coefs = ... weights = ... % Parallel filter + corner turn. Y(:,:) = conv2(coefs,X); % Parallel matrix multiply. Y(:,:) = weights*Y; % Finalize pMATLAB and exit. pMATLAB_Finalize; exit; Parallel performance Speedup Number of Processors • Matlab is the main specification language for signal processing • pMatlab allows parallel specifciations using same mapping constructs being developed for ||VSIPL++

  27. Outline • Introduction • Demonstration • Development • Applied Research • Future Challenges • Summary

  28. Optimal Mapping of Complex Algorithms Input Matched Filter Beamform Low Pass Filter XIN XOUT XIN XIN XOUT FFT XIN mult FIR1 FIR2 XOUT IFFT W4 W3 W1 W2 Application Different Optimal Maps Intel Cluster Workstation Embedded Multi-computer Embedded Board PowerPC Cluster Hardware • Need to automate process of mapping algorithm to hardware

  29. HPEC-SI Future Challenges Time End of 5 Year Plan Phase 5 Applied Research: Higher Languages (Java?) Phase 4 Development: Self-optimization Applied Research: PCA/Self-optimization prototype Phase 3 Demonstration: Hybrid Architectures Applied Research: Hybrid Architectures Development: Hybrid Architectures Hybrid VSIPL prototype Development: Fault tolerance Demonstration: Fault tolerance FT VSIPL Functionality Hybrid VSIPL Demonstration: Unified Comp/Comm Lib • Portability across • architectures • RISC/FPGA Transparency Fault Tolerant VSIPL Parallel VSIPL++ • Demonstrate • Fault Tolerance • Increased reliability • Unified Comp/Comm Standard • Demonstrate scalability

  30. Summary • HPEC-SI Program on track toward changing software practice in DoD HPEC Signal and Image Processing • Outside funding obtained for DoD program specific activities (on top of core HPEC-SI effort) • 1st Demo completed; 2nd selected • Worlds first parallel, object oriented standard • Applied research into task/pipeline parallelism; fault tolerance; parallel specification • Keys to success • Program Office Support: 5 Year Time horizon better match to DoD program development • Quantitative goals for portability, productivity and performance • Engineering community support

  31. Web LinksHigh Performance Embedded Computing Workshophttp://www.ll.mit.edu/HPECHigh Performance Embedded Computing Software Initiativehttp://www.hpec-si.org/Vector, Signal, and Image Processing Libraryhttp://www.vsipl.org/MPI Software Technologies, Inc.http://www.mpi-softtech.com/Data Reorganization Initiativehttp://www.data-re.org/CodeSourcery, LLChttp://www.codesourcery.com/MatlabMPIhttp://www.ll.mit.edu/MatlabMPI

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